View GWIXP455AAC_3876847.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

intel ? ixp45x and intel ? ixp46x product line of network processors datasheet product features for a complete list of product features, see ?product features? on page 9 . this document describes in full the features of the silicon. so me of these features re quire enabling software supplied by intel. please refer to the intel ? ixp400 software programmer?s guide for information on which features are enabled at this time. typical applications these features do not require enabling software ? intel xscale ? core ? up to 667 mhz ? pci v. 2.2 33/66 mhz (host/option) ? usb 1.1 device controller ? usb 2.0 host controller ? ddri sdram interface ? master/target capable expansion bus ? two uarts ? internal bus performance monitoring unit ? 16 gpio ? four internal timers ? synchronous serial protocol (ssp) port ? i 2 c interface ? spread spectrum clocking for reduced emi ? packaging ?544-pin pbga ?commercial/extended temperature ? lead-free support these features require enabling software. for information on which features are enabled at this time, see the intel ? ixp400 software programmer?s guide . ? cryptography unit (random number generator and exponentiation unit) ? encryption/authentication (aes/ aes-ccm/3des/des/sha-1/sha-256/ sha-384/sha-512/md-5) ? two high-speed, serial interfaces ? three network processor engines ? up to three mii interfaces ? up to six smii interfaces ? up to one utopia level 2 interface ? ieee-1588 hardware assist ? small-to-medium business router ? industrial controllers ? modular router ? access points (802.11a/b/g) ? network-attached storage ? wired/wireless rfid readers ? voip integrated access device (iad) ? video ip telephones ? security gateway/router ? network printers ? control plane ? mini-dslam document number: 306261-003 august 2005
august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 2 document number: 306261-003 information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel's terms and conditions of sale for such products, in tel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products includi ng liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instruct ions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local intel sales office or your distributor to obt ain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are refer enced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. anypoint, appchoice, boardwatch, bunnypeople, cableport, celeron, chips, ct media, dialogic, dm3, etherexpress, etox, flashfile , i386, i486, i960, icomp, instantip, intel, intel centrino, intel logo, intel386, intel486, intel740, inteldx2, inteldx4, intelsx2, intel cr eate & share, intel gigablade, intel inbusiness, intel inside, intel inside logo, intel netburst, intel netmerge, intel netstructure, intel play, intel play l ogo, intel singledriver, intel speedstep, intel strataflash, intel teamstation, intel xeon, intel xscale, iplink, itanium, mcs, mmx, mmx logo, optimizer logo, overdrive, paragon, pc dads, pc parents, pdcharm, pentium, pentium ii xe on, pentium iii xeon, performance at your command, remoteexpress, smartdie, solutions960, sound mark, storageexpress, the computer inside., the journey inside, tokenexpress , voicebrick, vtune, and xircom are trademarks or registered trademarks of intel corporation or it s subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2005, intel corporation
intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 3 contents contents 1.0 product features ........................................................................................................................... 9 1.1 product line features ....................................................................................................... ...9 1.2 model-specific features ..................................................................................................... 14 2.0 about this document ................................................................................................................. 15 3.0 functional overview ................................................................................................................... 15 3.1 key functional units ........................................................................................................ ...19 3.1.1 network processor engines (npes) ...................................................................... 19 3.1.2 internal bus............................................................................................................ 21 3.1.2.1 north ahb ..............................................................................................21 3.1.2.2 south ahb ............................................................................................. 21 3.1.2.3 memory port interface ........................................................................... 22 3.1.2.4 apb bus................................................................................................. 22 3.1.3 mii/smii interfaces................................................................................................. 22 3.1.4 utopia level 2 ..................................................................................................... 23 3.1.5 usb 1.1 device interface ...................................................................................... 23 3.1.6 usb 2.0 host interface .......................................................................................... 23 3.1.7 pci controller ........................................................................................................ 24 3.1.8 ddri sdram controller........................................................................................ 24 3.1.9 expansion interface ............................................................................................... 26 3.1.9.1 expansion bus legacy mode of operation............................................ 27 3.1.9.2 expansion bus enhanced mode of operation ....................................... 27 3.1.10 high-speed, serial interfaces ................................................................................ 28 3.1.11 uarts ................................................................................................................... 2 8 3.1.12 gpio ..................................................................................................................... .28 3.1.13 internal bus performanc e monitoring unit (ibpmu) .............................................. 29 3.1.14 interrupt contro ller ................................................................................................. 29 3.1.15 timers ................................................................................................................... .30 3.1.16 ieee 1588 hardware assistance........................................................................... 30 3.1.17 synchronous serial port interface ......................................................................... 30 3.1.18 i2c interface .......................................................................................................... 31 3.1.19 aes/des/sha/md-5 ................ ................ ................ ................ ................ ............. 31 3.1.20 cryptography un it .................................................................................................. 31 3.1.21 queue manager ..................................................................................................... 32 3.2 intel xscale ? core .............................................................................................................. 33 3.2.1 super pipeline ....................................................................................................... 34 3.2.2 branch target buffer ............................................................................................. 35 3.2.3 instruction memory management unit ... ................................................................ 35 3.2.4 data memory management unit ............................................................................ 36 3.2.5 instruction cache ................................................................................................... 36 3.2.6 data cache ............................................................................................................ 37 3.2.7 mini-data cache .................................................................................................... 37 3.2.8 fill buffer and pend buffe r..................................................................................... 37 3.2.9 write buffer ............................................................................................................ 38 3.2.10 multiply-accumulate coprocessor ......................................................................... 38 3.2.11 performance monitoring unit ................................................................................. 39
august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 4 document number: 306261-003 contents 3.2.12 debug unit............................................................................................................. 39 4.0 package information ................................................................................................................... 40 4.1 package description......................................................................................................... .. 40 4.1.1 package drawings................................................................................................. 40 4.1.2 package markings ................................................................................................. 43 4.1.3 part numbers......................................................................................................... 45 4.2 functional signal definitions .............................................................................................. 4 6 4.3 signal-pin descriptions..................................................................................................... .. 90 4.4 package thermal specifications ...................................................................................... 115 5.0 electrical specifications ........................................................................................................... 117 5.1 absolute maximum ratings .............................................................................................. 117 5.2 v ccpll1 , v ccpll2 , v ccpll3 , osc_vccp, osc_vcc pin requ irements ....................... 117 5.2.1 v ccpll1 requirement .......................................................................................... 117 5.2.2 v ccpll2 requirement .......................................................................................... 118 5.2.3 v ccpll3 requirement .......................................................................................... 118 5.2.4 osc_vccp requirement ................................................................................... 119 5.2.5 osc_vcc requirement...................................................................................... 119 5.3 rcomp pin requirements............................................................................................... 120 5.4 ddri_rcomp pin requirements .................................................................................... 121 5.5 dc specifications ........................................................................................................... .. 121 5.5.1 operating conditions ........................................................................................... 121 5.5.2 pci dc parameters ............................................................................................. 122 5.5.3 usb 1.1 dc parameters...................................................................................... 122 5.5.4 utopia level 2 dc parameters ......................................................................... 123 5.5.5 mii/smii dc parameters....................... ............................................................... 123 5.5.6 mdi dc parameters ............................................................................................ 124 5.5.7 ddri sdram bus dc parameters ..................................................................... 124 5.5.8 expansion bus dc parame ters ........................................................................... 125 5.5.9 high-speed, serial interface 0 dc parameters................................................... 125 5.5.10 high-speed, seri al interface 1 dc parameters................................................... 126 5.5.11 uart dc parameters ......................................................................................... 126 5.5.12 serial peripheral interface dc parameters.......................................................... 126 5.5.13 i2c interface dc parameters ............... ............................................................... 127 5.5.14 gpio dc parameters .......................................................................................... 127 5.5.15 jtag dc parameters.......................................................................................... 127 5.5.16 reset dc parameters.......................................................................................... 128 5.5.17 all remaining i/o dc parameters ........ ............................................................... 128 5.6 ac specifications........................................................................................................... ... 129 5.6.1 clock signal timings ........................................................................................... 129 5.6.1.1 processors? clock timings........... ........................................................ 129 5.6.1.2 pci clock timings ............................................................................... 130 5.6.1.3 mii/smii clock timings ........................................................................ 130 5.6.1.4 utopia level 2 clock timings ........................................................... 131 5.6.1.5 expansion bus clock timings ............................................................. 131 5.6.2 bus signal timings .............................................................................................. 132 5.6.2.1 pci ....................................................................................................... 132 5.6.2.2 usb 1.1 interface................................................................................. 133 5.6.2.3 utopia level 2 ................................................................................... 134 5.6.2.4 mii/smii................................................................................................ 135
intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 5 contents 5.6.2.5 mdio....................................................................................................138 5.6.2.6 ddri sdram bus ...............................................................................139 5.6.2.7 expansion bus .....................................................................................142 5.6.2.8 serial peripheral port interface timing ................................................158 5.6.2.9 i2c interface timing.............................................................................159 5.6.2.10 high-speed, serial interfaces ..............................................................161 5.6.2.11 jtag ....................................................................................................163 5.6.3 reset timings ......................................................................................................164 5.7 power sequence .............................................................................................................. 165 5.8 power dissipation ........................................................................................................... ..166 5.9 ordering information.......... .............................................................................................. .166 figures 1 intel ? ixp465 network processor bl ock diagram ...................................................................... 16 2 intel ? ixp460 network processor bl ock diagram ...................................................................... 17 3 intel ? ixp455 network processor bl ock diagram ...................................................................... 18 4 intel xscale ? core block diagram ............................................................................................. 34 5 544-pin lead pbga package ? first of two dr awings ............................................................ 41 6 544-pin lead pbga package ? second of tw o drawings....................................................... 42 7 package markings: intel ? ixp45x and intel ? ixp46x product line of network processors? extended and commercial temperature, lead-free / compliant with standard for restriction on the use of hazardous substances (rohs) ......................................................... 43 8 package markings: intel ? ixp45x and intel ? ixp46x product line of network processors ? commercial and extended temperature, lead-based .............................................................. 44 9v ccpll1 power filtering diagram ..... ........................................................................................118 10 v ccpll2 power filtering diagram ..... ........................................................................................118 11 v ccpll3 power filtering diagram ..... ........................................................................................119 12 osc_vccp power filtering diagram ................. .....................................................................119 13 osc_vcc power filtering diagram.................... .....................................................................120 14 rcomp pin external resistor requirements ..... .....................................................................120 15 ddri_rcomp pin external resistor requiremen ts................................................................121 16 typical connection to an oscillator .......................................................................................... 130 17 pci output timing ............................................................................................................ ........132 18 pci input timing ............................................................................................................. ..........132 19 utopia level 2 input timings .................................................................................................1 34 20 utopia level 2 output timings ..............................................................................................134 21 smii output timings .......................................................................................................... .......135 22 smii input timings........................................................................................................... .........136 23 source synchronous smii output timings...............................................................................136 24 source synchronous smii input timings .................................................................................137 25 mii output timings ........................................................................................................... ........137 26 mii input timings ............................................................................................................ ..........138 27 mdio output timings .......................................................................................................... .....138 28 mdio input timings........................................................................................................... .......139 29 ddri sdram write timings ....................................................................................................1 39 30 ddri sdram read timings (2.0 cas latency) .....................................................................140 31 ddri sdram read timings (2.5 cas latency) .....................................................................141
august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 6 document number: 306261-003 contents 32 expansion bus synchronous timing ................... ..................................................................... 142 33 intel multiplexed mode....................................................................................................... ....... 143 34 intel simplex mode ........................................................................................................... ........ 144 35 motorola* multiplexed mode ................................................................................................... .. 146 36 motorola* simplex mode ....................................................................................................... ... 148 37 hpi*?8 mode write accesses .................................................................................................. 1 49 38 hpi*-16 multiplexed write mode .............................................................................................. 1 52 39 hpi*-16 multiplexed read mode .............................................................................................. 15 3 40 hpi*-16 non-multiplexed read mode ...................................................................................... 154 41 hpi*-16 non-multiplexed write mode....................................................................................... 156 42 i/o wait normal phase timing ................................................................................................. 157 43 i/o wait extended phase timing ............................................................................................. 15 8 44 serial peripheral interface timing ........................................................................................... .158 45 i2c interface timing ......................................................................................................... ........ 159 46 high-speed, serial timings .... ............................................................................................... ... 161 47 boundary-scan general timings ........................ ..................................................................... 163 48 boundary-scan reset timings .. ............................................................................................... 1 63 49 reset timings................................................................................................................ ........... 164 50 power-up sequence timing ..................................................................................................... 165 tables 1 intel ? ixp45x and intel ? ixp46x product line of network processors features ...................... 14 2 related documents ............................................................................................................. ....... 15 3 network processor functions................................................................................................... .. 19 4 supported ddri memory configurations ................................................................................... 25 5 gpio alternate function table ................................................................................................. .29 6 intel ? ixp46x product line part nu mbers: lead (pb) packaging . ............................................. 45 7 intel ? ixp46x product line part nu mbers: lead free (pb-free) packaging .............................. 45 8 intel ? ixp45x product line part nu mbers: lead (pb) packaging . ............................................. 46 9 intel ? ixp45x product line part nu mbers: lead free (pb-free) packaging .............................. 46 10 signal type definitions...................................................................................................... ......... 46 11 ddr sdram interface .......................................................................................................... ..... 49 12 pci controller ............................................................................................................... .............. 51 13 high-speed, serial in terface 0 ............................................................................................... .... 56 14 high-speed, serial in terface 1 ............................................................................................... .... 58 15 utopia level 2/mii_a/ smii[4] interface ................................................................................... 60 16 mii/smii interfaces .......................................................................................................... ........... 69 17 expansion bus interface...................................................................................................... ....... 77 18 uart interfaces .............................................................................................................. ........... 80 19 serial peripheral port inte rface ............................................................................................. ..... 82 20 i2c interface ................................................................................................................ ............... 83 21 usb host/device interfaces ................................................................................................... .... 84 22 oscillator interface......................................................................................................... ............. 85 23 gpio interface............................................................................................................... ............. 86 24 jtag interface ............................................................................................................... ............ 87 25 system interface............................................................................................................. ............ 87 26 power interface .............................................................................................................. ............ 89 27 processors? ball map assignments ............................................................................................ 9 0 28 2.8-watt maximum power dissipation................. ..................................................................... 116
intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 7 contents 29 3.3-watt maximum power dissipation......................................................................................116 30 4.0-watt maximum power dissipation......................................................................................116 31 operating conditions ......................................................................................................... .......121 32 pci dc parameters ............................................................................................................ ......122 33 usb 1.1 dc parameters........................................................................................................ ...122 34 utopia level 2 dc parameters ..............................................................................................123 35 mii/smii dc parameters....................................................................................................... ....123 36 mdi dc parameters ............................................................................................................ .....124 37 ddri sdram bus dc parameters ..........................................................................................124 38 expansion bus dc parameters ................................................................................................12 5 39 high-speed, serial interface 0 dc parameters... .....................................................................125 40 high-speed, serial interface 1 dc parameters... .....................................................................126 41 uart dc parameters ........................................................................................................... ...126 42 serial peripheral interface dc parameters ...... ........................................................................126 43 i2c interface dc parameters ........................ .......................................................................... .127 44 gpio dc parameters ........................................................................................................... ....127 45 jtag dc parameters........................................................................................................... ....127 46 pwron_reset _n and reset_in_n parameters. ................ ............. ............. ............ ........128 47 all remaining i/o dc parameters (jtag, pll_lock) ...........................................................128 48 devices? clock timings....................................................................................................... ......129 49 processors? clock timings spread spectrum pa rameters.......................................................129 50 pci clock timings ............................................................................................................ ........130 51 mii/smii clock timings....................................................................................................... ......130 52 utopia level 2 clock timings ........................... .....................................................................13 1 53 expansion bus clock timings .................................................................................................. 131 54 pci bus signal timings ....................................................................................................... .....133 55 utopia level 2 input timings values .....................................................................................134 56 utopia level 2 output timings values ..................................................................................135 57 smii output timings values ................................................................................................... ..135 58 smii input timings values.................................................................................................... ....136 59 source synchronous smii output timings values...................................................................136 60 source synchronous smii input timings values .....................................................................137 61 mii output timings values .................................................................................................... ...137 62 mii input timings values ..................................................................................................... .....138 63 mdio timings values.......................................................................................................... .....139 64 ddri sdram write timings values ........................................................................................140 65 ddri sdram read timing values..........................................................................................141 66 expansion bus synchronous operation timing values ...........................................................142 67 intel multiplexed mode values.......................... ...................................................................... ..143 68 intel simplex mode values .................................................................................................... ...145 69 motorola* multiplexed mode values .........................................................................................146 70 motorola* simplex mode values...............................................................................................1 48 71 hpi* timing symbol description............................................................................................... 150 72 hpi*?8 mode write accesses values.......................................................................................150 73 setup/hold timing values in asynchronous mode of operation..............................................151 74 hpi*-16 multiplexed write acce sses values ............................................................................151 75 hpi*-16 multiplexed read accesses values ....... .....................................................................152 76 hpi-16 non-multiplexed read accesses values......................................................................154 77 hpi-16 non-multiplexed write accesses values. .....................................................................155 78 serial peripheral port interface timing values.........................................................................159
august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 8 document number: 306261-003 contents 79 i2c interface timing values .................................................................................................. ... 159 80 high-speed, serial timing va lues............................................................................................ 1 62 81 boundary-scan interface timings values ........... ..................................................................... 163 82 reset timings table parameters ............................................................................................. 16 4 83 power dissipation values ..................................................................................................... .... 166 84 power dissipation test conditions ........................................................................................... 1 66 revision history date revision description august 2005 003 table 1 , table 6 , and table 7 : removed intel ? ixp465 667 mhz extended temperature part offering. section 3.2.11 : corrected number of pmu 32-bit event counters to 4. section 4.1.3 : updated part number tables with new a1 stepping values. table 13 : updated hss_txdata0 and hss_txclk0 description. table 14 : updated hss_txdata1 description. table 17 : changed ex_addr[24:0] pull-down value to 4.7 k ? . table 26 : added 1.5 v information. table 28 and table 29 : clarified table footnote. section 5.0 , figure 12 , figure 13 , table 31 : corrected supply voltage names for osc_vcc, osc_vccp, osc_vss, and osc_vssp. table 30 : added new table for 4.0 w power. table 31 and table 83 : changed 1.4 v to 1.5 v for intel ? ixp465 667 mhz processor. table 51 : replaced t rise-fall with frequency tolerance. section 5.6.2.7.3 : added new figures for using ex_iowait_n. table 64 : corrected t3 and t4 values. may 2005 002 added support for intel ? ixp455 network processor including table 1 on page 14 , figure 3 on page 18 , table 27 on page 89 , and table 83 on page 165 . section 4.0, ?package information? on page 40 : added ?package markings? and ?part numbers? sections. table 11 on page 48 : enhanced description of ddri_cb[7:0]. table 50 on page 129 : added t slew rate information. march 2005 001 initial release of document.
product features intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 9 1.0 product features 1.1 product line features note: this document discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. a subset of these f eatures is supported by cer tain processors in the ixp45x/ixp46x product line, such as the intel ? ixp460 or intel ? ixp455 network processors. for details on feature support listed by processor, see table 1 on page 14 . some of the features described in this document re quire software delivered by intel. some features may not be enabled with current software rel eases. the features which require software are identified within this document. please refer to the intel ? ixp400 software programmer?s guide for information on which featur es are enabled at this time. ? intel xscale ? core (compliant with intel ? strongarm * architecture) ? high-performance processor based on intel xscale ? microarchitecture ? seven/eight-stage intel ? super-pipelined risc technology ? memory management unit (mmu) ? 32-entry, data memory management unit ? 32-entry, instruction memory management unit (mmu) ? 32-kbyte, 32-way, set as sociative instruction cache ? 32-kbyte, 32-way, set associative data cache ? 2-kbyte, two-way, set as sociative mini-data cache ? 128-entry, branch target buffer ? eight-entry write buffer ? four-entry fill and pend buffers ? clock speeds: ? 266 mhz ? 400 mhz ? 533 mhz ? 667 mhz (not supported on intel ? ixp455 network processor) ?intel ? strongarm * version 5te compliant ?intel ? media processing technology multiply-accumulate coprocessor ? debug unit accessible through jtag port ? pci interface ? 32-bit interface ? selectable clock ? 33-mhz clock output produced by gpio15 ? 1- to 66-mhz clock input ? pci local bus specification , revision 2.2 compatible
product features august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 10 document number: 306261-003 ? pci arbiter supporting up to four exte rnal pci devices (four req/gnt pairs) ? host/option capable ? master/target capable ? two dma channels ? usb 1.1 device controller ? full-speed capable ? embedded transceiver ? 16 endpoints ? usb 2.0 host controller ? low-speed and full-speed capable ? embedded transceiver ? ehci compliant ? separate interface from usb 1.1 device controller ? ddri-266 sdram interface ? internally multi-ported memory cont roller unit (three internal ports) ? 32-bit data ? 13-bit address ? 133.32 mhz (which is 4 * osc_in input pin) ? supports 128/256/512/1,024-mbit technologies ? unbuffered ddri sdram support only ? up to eight open pages simultaneously maintained ? support for 32 mbyte, minimum; 1 gbyte, maximum ? user-enabled, single-bit error correction/multi-bit error detection ecc support (ecc not supported on intel ? ixp455 network processor) ? expansion interface ? master/target interface ? 25-bit address ? 32-bit data ? eight programmable outbound chip selects ? one inbound chip select ? four request/grant pairs ? outbound transfers (ixp45x/ixp46x network pro cessors are the master to external target devices) ? inbound transfers (ixp45x/ixp46x network pro cessors are a target to external masters) ? bus tri-state for sideband tr ansfers (external masters accesses to external target device) ? outbound transfer support
product features intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 11 ? supports intel/motor ola* microprocessors ? multiplexed-style bus cycles ? simplex-style bus cycles ? dsp support for texas instruments* dsps supporting hpi*-8 bus cycles ? dsp support for texas instruments dsps supporting hpi-16 bus cycles ? synchronous flash support ? flow through zbt sram burst support ? up to 80-mhz operation at 40 pf load ? supports even/odd-parity generation and checking in all extended modes and in some legacy modes (intel and mo torola style bus cycles) ? inbound transfer support ? single transfer or burst support ? cryptography unit ? exponentiation unit (eau) ? random number generator (rng) ? secure hash algorithm (sha) ? two uart interfaces ? 1,200 baud to 921 kbaud ? 16550 compliant ? 64-byte tx and rx fifos ? cts and rts modem-control signals ? synchronous serial port interface ? master mode only ? motorola?s serial peri pheral interface (spi) ? national?s microwire* ? texas instruments? synchronous serial protocol (ssp) ? i 2 c interface ? multi-master capable ? slave capable ? fast-mode support 400 kbps ? slow-mode support 100 kbps ? internal bus performance monitoring unit (ibpmu) ? seven 27-bit event counters ? monitoring of internal-bus o ccurrences and duration events ? 16 gpios ? four internal timers ? watchdog timer ? general-purpose timer
product features august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 12 document number: 306261-003 ? two one-shot timers ? packaging ?544-pin pbga ? commercial temperature (0 to 70 c) ? extended temperature (-40 to 85 c) ? lead free support the remaining features described in the product line features list require software in order for these features to be functional. to de termine if the feature is enabled, see the intel ? ixp400 software programmer?s guide . ? three network processor engines (npes) note 1 used to off load typical layer-2 networking functions such as: ? ethernet filtering ?atm saring ?hdlc ? layer-2 switching ? security acceleration (aes/des3/sha/md-5) ? configurable network interface, conf igurable in the following manner: notes 1, 3 ? three mii/smii/ss-smii interfaces ? two mii/smii/ss-smii interface + 1 utopia level 2 interface ? one mii/smii/ss-smii interface + 1 utop ia level 2 interface + four smii/ss-smii interfaces ? two mii/smii/ss-smii interfaces + four smii/ss-smii interfaces ? mii/smii/ss-smii interfaces are: note 1 ? 802.3 mii interfaces that additiona lly support smii/s s-smii interfaces ? single mdio interface to contro l the mii/smii/ss-smii interfaces ? utopia level 2 interface is: note 1 ? eight-bit interface ? up to 33-mhz clock speed ? five transmit and five receive address lines ? encryption/authentication note 1 ?des ?des3 ? aes 128-bit and 256-bit ? single-pass aes-ccm ? sha-1, sha-256, sha-384, sha-512 ?md-5 ? two high-speed, serial interfaces note 1
product features intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 13 ? six-wire ? supports speeds up to 8.192 mhz ? supports connection to t1/e1 framers ? supports connection to codec/slics ? eight hdlc channels ? clock source provided from an external source or internal hss clock divider ? ieee 1588 hardware assistance notes 2, 3 ? time master support ? time target support notes: 1. this feature requires intel supplied software. to determine if this feature is enabled by a particular software release, see the intel ? ixp400 software programmer?s guide . 2. although this feature has dir ect access from the intel xscale ? core, this feature monitors the activity of the mii interfaces which requi res intel-supplied software to operate. 3. four smii/ss-smii interfaces and ieee 1588 ha rdware assistance are not available for the intel ? ixp455 network processor.
product features august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 14 document number: 306261-003 1.2 model-specific features table 1. intel ? ixp45x and intel ? ixp46x product line of network processors features feature intel ? ixp465 intel ? ixp460 intel ? ixp455 processor speed (mhz) 266 / 400 / 533 / 667 266 / 400 / 533 / 667 266 / 400 / 533 gpio xxx uart 0/1 xxx hss 0 (npe-a) ? xx hss 1 (npe-a) ? xx utopia 2/ mii / smii (npe a) ? xx mii / smii / 4-port smii (npe b) ? xx ?? mii / smii (npe c) ? xxx usb 1.1 device controller x x x usb 2.0 host controller x x x pci 32-bit, up to 66-mhz 32-bit, up to 66-mhz 32-bit, up to 66-mhz expansion bus 32-bit or 16-bit, 80-mhz, host support, parity support 32-bit or 16-bit, 80-mhz, host support, parity support 32-bit or 16-bit, 80-mhz, host support, parity support ddri-266 sdram 32-bit, 133-mhz clock with ecc 32-bit, 133-mhz clock with ecc 32-bit, 133-mhz clock without ecc aes / aes-ccm/ des / des3 ? xx cryptography unit x x multi-channel hdlc ? 88 sha / md-5 ? xx ieee1588 hardware assistance x x i 2 c xxx ssp x x x commercial temperature x x x extended temperature x ??? x ??? x ? these features require intel-supplied software in or der to be operational. to determine if the feature is enabled, see the intel ? ixp400 software programmer?s guide . ?? 4-port smii is not supported on the ixp455 network processor. ??? extended temperature is not available on intel ? ixp465 or intel ? ixp460 at 667 mhz.
about this document intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 15 2.0 about this document this datasheet contains a func tional overview of the intel ? ixp45x and intel ? ixp46x product line of network processors, as well as mechani cal data (package signal locations and simulated thermal characteristics), ta rgeted electrical specifi cations, and some bus functional wave forms for the device. detailed functional descriptions ? other than parametric performance ? are published in the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual . other related documents are shown in table 2 . 3.0 functional overview the intel ? ixp45x and intel ? ixp46x product line of network processors are compliant with the intel ? strongarm * version 5te instruction-set architect ure (isa). the ixp45x/ixp46x network processors are designed with intel, 0.18-micron semiconductor process technology. this process technology ? along with the compactness of the intel ? strongarm * risc isa, the ability to simultaneously process data with up to three in tegrated network processing engines (npes), and numerous dedicated-func tion peripheral interfaces ? enables the ixp45x/ixp46x network processors to operate over a wide range of low- cost networking applications with industry-leading performance. as indicated in figure 1 , figure 2 , and figure 3 , the ixp45x/ixp46x network processors combine many features with the intel xscale ? core to create a highly integr ated processor applicable to lan/wan-based networking applications in addition to other embedded networking applications. this section briefly describes the main features of the product. for detailed functional descriptions, see the intel ? ixp45x and intel ? ixp46x product line of ne twork processors developer?s manual . table 2. related documents document title document # intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual 306262 intel? ixp45x and intel? ixp46x product line of network processors hardware design guidelines 305261 intel ? ixp4xx product line of network processors specification update 306428 intel ? ixp400 software programmer?s guide 252539 intel xscale ? core developer?s manual 273473 intel xscale ? microarchitecture technical summary ? pci local bus specification , revision 2.2 n/a universal serial bus specification , revision 1.1 n/a ddr sdram specification n/a
functional overview august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 16 document number: 306261-003 figure 1. intel ? ixp465 network processor block diagram uart 1 921 kbaud uart 0 921 kbaud ibpmu interrupt controller gpio timers ieee 1588 usb device version 1.1 ssp i 2 c 16 gpio npe a npe b npe c aes/des/sha/ md-5 hss 0 hss 1 utopia 2/mii/smii mii/quad smii mii/smii intel xscale ? core 32-kbyte i-cache 32-kbyte d-cache 2-kbyte mini d-cache ddri memory controller unit 32 bit + ecc mpi 133 mhz x 64 ahb/ahb bridge pci controller expansion bus controller usb-host controller v. 2.0 high-speed is not supported queue manager ahb slave / apb master bridge south ahb 133.32 mhz x 32 bits south ahb arbiter north ahb arbiter master on south ahb master on north ahb north ahb 133.32 mhz x 32 bits apb 66.66 mhz x 32 bits cryptography unit hardware rng exponentiation unit 32 bit at 33/66 mhz 8/16/32 bit + parity bus arbiters slave only ahb slave / apb master b3777 -006
functional overview intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 17 figure 2. intel ? ixp460 network processor block diagram uart 1 921 kbaud uart 0 921 kbaud pmu interrupt controller gpio timers ieee 1588 usb device version 1.1 ssp i 2 c 16 gpio npe b npe c mii/smii mii/smii intel xscale ? core 32-kbyte i -cache 32-kbyte d-cache 2-kbyte mini d-cache ddri memory controller unit 32 bit + ecc mpi 133 mhz x 64 ahb/ahb bridge pci controller expansion bus controller usb-host controller v2.0 high speed is not supported queue manager ahb slave / apb master bridge south ahb 133 mhz x 32 bits south ahb arbiter north ahb arbiter master on south ahb master on north ahb north ahb 133mhz x 32 bits apb 66 mhz x 32 bits public key exchange crypto engine ? ahb-pke bridge ? random number generator (rng) ? exponentiation acceleration unit (eau) ? secure hash algorithm unit (sha) 32 bit at 33/66 mhz 16/32 bit + parity bus arbiters slave only ahb slave / apb master b4822 -01
functional overview august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 18 document number: 306261-003 figure 3. intel ? ixp455 network processor block diagram uart 1 921 kbaud uart 0 921 kbaud ibpmu interrupt controller gpio timers usb device version 1.1 ssp i 2 c 16 gpio npe a npe b npe c aes/des/sha/ md-5 hss 0 hss 1 utopia 2/mii/smii mii/smii mii/smii intel xscale ? core 32-kbyte i -cache 32-kbyte d-cache 2-kbyte mini d-cache max speed = 533 mhz ddri memory controller unit 32 bit with no ecc mpi 133 mhz x 64 ahb/ahb bridge pci controller expansion bus controller usb-host controller v. 2.0 high-speed is not supported ahb slave / apb master bridge south ahb 133.32 mhz x 32 bits south ahb arbiter north ahb arbiter master on south ahb master on north ahb north ahb 133.32 mhz x 32 bits apb 66.66 mhz x 32 bits cryptography unit hardware rng exponentiation unit 32 bit at 33/66 mhz 8/16/32 bit + parity bus arbiters slave only ahb slave / apb master b5024 -001 bv queue manager
functional overview intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 19 3.1 key functional units the following sections briefly describe the functi onal units and their interaction in the system. for more detailed information, refer to the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual . unless otherwise specified, the functional descri ptions apply to all of the ixp45x/ixp46x network processors. for specific informa tion on supported in terfaces, refer to table 1 on page 14 . for model-specific block diagrams, see figure 1 on page 16 , figure 2 on page 17 , and figure 3 on page 18 . 3.1.1 network processor engines (npes) the network processor engines (npes) are dedi cated-function processors containing hardware coprocessors integrated into th e ixp45x/ixp46x network processo rs. the npes are used to off load processing function required by the intel xscale core. these npes are high-perf ormance, hardware-multi -threaded processors with additional local- hardware-assist functionality used to off load highly processor-intensive functions such as mii (mac), crc checking/generation, aal 2 segmenta tion and re-assembly, aes, aes-ccm, des, des3, sha-1/256/384/512, md5, etc. all instruction code for the npes are stored local ly and is accessed using a dedicated instruction memory bus. likewise, a separate dedicated data memory bus allows accesses to local code store as well as ddr sdram via the ahb bus. these npes support processing of the dedicated peripherals that can include: ? one utopia level 2 (universal test and operation phy interface for atm) interface ? two high-speed serial (hss) interfaces ? up to three media-independent interface (mii), up to six serial media independent interfaces (smii)/source-synchronous se rial media independent inte rfaces (ss-smii), or some combination of each. table 3 specifies the possible combination of inte rfaces for the npes co ntained on the ixp45x/ ixp46x network processors. these configurations are determined by the factory programmed fuse settings or by software that configures the part during boot-up. table 3. network processor functions (sheet 1 of 2) device utopia hss mii /smii a mii / 4 smii b mii / smii c aes / des / des3 hdlc sha md-5 configuration 0 (default) xx mii mii x 8 x configuration 1 x x smii mii x 8 x configuration 2 x x smii smii x 8 x configuration 3 x x 4 smii mii x 8 x configuration 4 x x 4 smii smii x 8 x configuration 5 x mii mii mii x 8 x configuration 6 x mii smii mii x 8 x
functional overview august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 20 document number: 306261-003 the npe core is a hardware-multi-threaded proce ssor engine that is used to accelerate functions that are difficult to achieve high performance in a standard risc processor. each npe core is a 133.32-mhz (which is 4 * osc_in input pin) pro cessor core that has self-contained instruction memory and self-contained data memory that operat e in parallel. each npe core has 4 k words of instruction memory and 4 k words of data memory. in addition to having separate instruction/data me mory and local-code store, the npe core supports hardware multi-threading with support for multi ple contexts. the support of hardware multi- threading creates an efficient pro cessor engine with minimal processo r stalls due to the ability of the processor core to switch contexts in a sing le clock cycle, based on a prioritized/preemptive basis. the prioritized/preemptive na ture of the context switching a llows time-critical applications to be implemented in a low-latency fashion ? which is required when processing multi-media applications. the npe core also connects to several hardware-b ased coprocessors that are used to implement functions that are difficult for a processor to implemen t. these functions include: these coprocessors are implemented in hard ware, enabling the copr ocessors and the npe processor core to operate in parallel. with the addition of the new switching copro cessor (swcp) and the et hernet coprocessors, functions like a four-port, layer- 2 switch can be easily implemente d using all intel-based silicon. also, by using npes to implement switching func tions, value added features like vlan or ip switching can be easily upgraded using existing sili con. therefore, speeding up the end customer?s time to market while keeping product costs the same. the combined forces of the hardware multi-thr eading, local-code store, independent instruction memory, independent data memory, and parallel processing ? contained on the npe ? allows the intel xscale core to be utilized for application purposes. the mu lti-processing cap ability of the peripheral interface functions allo ws unparalleled performance to be achieved by the application running on the intel xscale core. configuration 7 x mii smii smii x 8 x configuration 8 x mii 4 smii mii x 8 x configuration 9 x mii 4 smii smii x 8 x configuration 10 x smii 4 smii smii x 8 x configuration 11 x smii smii smii x 8 x configuration 12 x smii smii mii x 8 x configuration 13 x smii 4 smii mii x 8 x table 3. network processor functions (sheet 2 of 2) device utopia hss mii /smii a mii / 4 smii b mii / smii c aes / des / des3 hdlc sha md-5 ? hss serialization/ de-serialization ? crc checking/generation ? des/des3/aes ? sha-1/256/384/512 ? md-5 ? hdlc bit stuffing/de-stuffing ? learning/filtering cont ent addressable memory ? media access controller functionality ? utopia level 2 framing
functional overview intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 21 3.1.2 internal bus the internal bus architecture of the ixp45x/ixp46x network processors are designed to allow parallel processing to occur and to isolate bus uti lization, based on particular traffic patterns. the bus is segmented into four major buses: 3.1.2.1 north ahb the north ahb is a 133.32-mhz (which is 4 * osc_in input pin), 32-bit bus that can be mastered by the npe a, npe b, or npe c. the targets of the north ahb can be the ddri sdram or the ahb/ahb bridge. the ahb/ahb bri dge allows the npes to access the peripherals and internal targets on the south ahb. data transfers by the npes on the north ahb to th e south ahb are targeted predominately to the queue manager. transfers to the ahb/ahb bridge may be ?posted? ? when writing ? or ?split? ? when reading. when a transaction is ?posted,? a master on the north ahb requests a write to a peripheral on the south ahb. if the ahb/ah b bridge has a free fifo location, th e write request will be transferred from the master on the north ahb to the ahb/ ahb bridge. the ahb/ahb bridge will complete the write on the south ahb, when it can obtain access to the peripheral on the south ahb. the north ahb is released to complete another transaction. when a transaction is ?split,? a master on the no rth ahb requests a read of a peripheral on the south ahb. if the ahb/ahb bridge has a free fifo location, the read request will be transferred from the master on the north ahb to the ahb/ ahb bridge. the ahb/ahb bridge will complete the read on the south ahb, when it can obtain access to the peripheral on the south ahb. once the ahb/ahb bridge has obtained the read information from the peripheral on the south ahb, the ahb/ahb bridge notifies the arbiter, on the north ahb, that the ahb/ahb bridge has the data for the master that requested the ?split? transfer. the master on the north ahb ? that requested the split transfer ? will arbitrate for the north ahb and tr ansfer the read data from the ahb/ahb bridge. the north ahb is released to complete another transaction while the north ahb master ? that requested the ?split? tr ansfer ? waits for the data to arrive. these ?posting? and ?splitting? tr ansfers allow control of the north ahb to be given to another master on the north ahb ? enabling the north ah b to achieve maximum ef ficiency. transfers to the ahb/ahb bridge are considered to be small and infrequent, relative to the traffic passed between the npes and the ddri sdram on the north ahb. when multiple masters arbitrate fo r the north ahb, the masters ar e awarded access to the bus in a round-robin fashion. each transaction can be no longer than an eight-word burst. this implementation promotes fairness within the system. 3.1.2.2 south ahb the south ahb is a 133.32-mhz (which is 4 * osc_in input pin), 32-bit bus that can be mastered by the intel xscale core, pci controller, expansi on bus interface, usb host controller, and the ahb/ahb bridge. the targets of the south ahb bus can be the ddri sdram, pci controller, queue manager, expansion bus, or the ahb/apb bridge. as a special case, the intel xscale ? core is the only master which can access the cryptography unit (target). ? north advanced, high-performance bus (ahb) ? memory port interface ? south ahb ? advanced peripheral bus (apb)
functional overview august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 22 document number: 306261-003 accesses across the apb/ahb bridge allows interfaci ng to peripherals att ached to the apb. the expansion bus and pci controller can be configured to support split transfers. arbitration on the south ahb are round-robin. each transaction can be no longer than an eight- word burst. this implementation pr omotes fairness within the system. 3.1.2.3 memory port interface the memory port interface (mpi) is a 128-bit bus that provides the intel xscale core a dedicated interface to the ddri sdram. the memory port interface operates at 133 .32 mhz (which is 4 * osc_in input pin). the memory port in terface stores memory trans actions from the intel xscale core which have not been processed by the memory controller. th e memory port interface supports eight core processor read transactions up to 32 bytes each . that total equals th e maximum number of outstanding transaction the core processor bus c ontroller can support. (t hat includes core dcu [4 - load requests to unique cache lines], ifu [2 - prefetch], imm [1 - tablewalk], dmm [1 - tablewalk].) the memory port interface also supports eight core-processor-posted write transactions up to 16 bytes each. arbitration on the memory port in terface is not required due to no contention with other masters. arbitration will exist in the ddri memory controller between all of the main internal busses. 3.1.2.4 apb bus the apb bus is a 66.66-mhz (which is 2* osc_in input pin), 32-bit bus that can be mastered by the ahb/apb bridge only. the targets of the apb bus can be: the apb interface is also used as an alternate-path interface to the npes and is used for npe code download and configuration. no arbitration is requ ired due to a single master implementation. 3.1.3 mii/smii interfaces the ixp45x/ixp46x network processors can be conf igured to support up to three mii, up to six smii/ss-smii in dustry-standard, or some co mbination thereof, media- independent interface (mii) interfaces. these interfaces are integrated into the ixp45x/ixp46x netw ork processors with separate media-access controllers and in many cases independent network pr ocessing engines. (see table 3 for allowable combinations.) ? usb 1.1 device controller ? uarts ? the internal bus performance monitoring unit (ibpmu) ? all npes ? gpio ? interrupt controller ? ieee 1588 hardware assist ? timers ? i 2 c ? serial peripheral port interface
functional overview intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 23 the independent npes and macs al low parallel processing of data traffic on the mii interfaces and off loading of processing required by the intel xscale core. the ixp45x/ixp46x network processors are compliant with the ieee 802.3 specification. in addition to the mii interfaces, the ixp45x /ixp46x network processors include a single management data interface that is used to confi gure and control phy devices that are connected to the mii interfaces. the ixp45x/i xp46x network processors prov ide support for serial media independent interface (smii). 3.1.4 utopia level 2 the integrated utopia le vel 2 interface works with a network- processing engine core for several of the ixp45x/ixp46x network processors. th e pins of the utopia level 2 interface are multiplexed with one of th e mii/smii interfaces. (see table 3 for details.) the utopia level 2 interface supports a single- or a multiple-physical-i nterface configuration with cell-level or octet-level handshaking. th e network processing engine handles segmentation and reassembly of atm cells, crc checking/genera tion, and transfer of data to/from memory. this allows parallel processing of data traffic on the utopia le vel 2 interface, off-loading these processing tasks from the intel xscale core. the ixp45x/ixp46x network processors are compliant with the atm forum , utopia level 2 specification , revision 1.0. 3.1.5 usb 1.1 d evice interface the integrated usb 1.1 device in terface supports full-speed op eration and 16 endpoints and includes an integrated transceiver. there are: ? six isochronous endpoints (three input and three output) ? one control endpoints ? three interrupt endpoints ? six bulk endpoints (three input and three output) 3.1.6 usb 2.0 host interface usb host functionality is implemented on the ixp45x/ixp46x network processors. the function being performed is defined by the usb 2.0 specificat ion, maintained by usb.org and the interface is (largely) ehci compliant, as defined by intel. not all features defined by the 2.0 specificatio n are supported for this implementation. the following is a partial list of supported features: ? host function ? low-speed interface ? full-speed interface ? ehci register interface
functional overview august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 24 document number: 306261-003 the following is a partial list of features not supported: ? device function ? otg function ? high-speed interface 3.1.7 pci controller the ixp45x/ixp46x network processors? pc i controller is compatible with the pci local bus specification , rev. 2.2. the pci interface is 32-bit co mpatible bus and capable of operating as either a host or an option (i.e. not the host). this pci implementation supports 3.3 v i/o only. 3.1.8 ddri sdram controller the ixp45x/ixp46x network pro cessors integrate a high-perfo rmance, multi-ported memory controller unit (mcu) to provide a direct interface between the ixp45x/ixp46x network processors and their local memory subsystem. the mcu supports: ? ddri 266 sdram ? 128/256/512-mbit, 1-gbit ddri sdram technology support ? only unbuffered dram support (no registered dram support) ? dedicated port for intel xscale core to ddr sdram ? between 32 mbyte and 1 gbyte of 32-bit ddr sdram for low-cost solutions ? single-bit error correction, multi-bit detection support (ecc) ? 32-, 40-bit wide me mory interfaces (non -ecc and ecc support) the ddri sdram interface provides a direct c onnection to a high-ban dwidth and reliable memory subsystem. the ddri sdram in terface is a 32-bit-wide data path. an 8-bit error correction code (ecc) across each 32-bit word improves syst em reliability. it is important to note that ecc is al so referred to as cb in many dimm specifications. the pins on ixp45x/ixp46x network processors are called ddri _cb[7:0]. the controller supports the 8 bits due to the fact that internally it is a 32- or 64-bit controller. however, this implementation of the controller only supports 32 bits. note: the ixp455 network processor does not support ecc functionality. the ecc circuitry was designed to operate always on a 64-bit word and when operating in 32-bit mode, the upper 32 bits are driven to zeros intern ally. to summarize the impact to the customer, the full 8 bits of ecc must be stored and read from a memory array in order for the ecc logic to work. an 8-bit-wide memory must be used when implementing ecc. the memory controller only corr ects single bit ecc errors on read cycles. the ecc is stored into the ddri sdram array along with the data and is checked when the data is read. if the code is incorrect, the mcu corrects the data (if possible) before reaching the ini tiator of the read. ecc error scrubbing must be done with software. user-d efined fault correction software is responsible for scrubbing the memory array and handling double-bit errors.
functional overview intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 25 in order to limit double-bit errors from occurri ng, periodically reading th e entire usable memory array will allow the hardware unit within the me mory controller to corr ect any single-bit, ecc errors that may have occurred prior to these errors becoming double-bit ecc errors. using this method is system-dependent. it is important to note as well, that when sub- word writes (byte writes or half-word writes) to a 32-bit memory with ecc enabled, the memory controller will implement read-modify writes. implementing read-modify writes is important to understand when understanding performance implications when writing software. to understand a read-modify write, understanding that a byte to be written falls within a 32-bit word which is addressed on a word-aligned boundary. when a byte write is requested, the memory controller will read the 32-bit word which encompasses the byte that is to be written. the memory controller will then modify the specified byte, calculate a new ecc, and then write the entire 32-bit word back into the memory location it was read from. the value written back into the memory location will contain the 32-bit word with the modified byte and the new ecc value. the mcu supports two banks of ddr sdram. the mcu has support for unbuffered ddri 266 only. table 4 illustrates the supported ddr sdram configurations for the ixp45x/ixp46x network processors. the 128/256/512-mbit, 1-gbit ddri sdram devices comprise four internal leaves. the mcu controls the leaf selects within 128/256/512-mbit, 1-gbit ddri sdram by toggling ddri_ba[0] and ddri_ba[1]. the two ddr sdram chip enables (ddri_cs[1:0]#) support a ddri sdram memory subsystem consisting of two banks. the base address for the two contiguous banks are programmed in the ddr sdram base register (sdbr) and must be aligned to a 32-mbyte boundary. the size of each ddr sdram bank is programmed with the ddr sdram boundary registers (sbr0 and sbr1). table 4. supported ddri memory configurations (sheet 1 of 2) ddri sdram technology ddri sdram arrangement # banks address size leaf select total memory size 1 page size 2 row col ddri_ba[1] ddri_ba[0] 128 mbit 16m x 8 1 12 10 i_ad[26] i_ad[25] 64 mbyte 4k 2 128 mbyte 4k 8m x 16 1 12 9 i_ad[25] i_ad[24] 32 mbyte 2k 2 64 mbyte 2k 256 mbit 32m x 8 1 13 10 i_ad[27] i_ad[26] 128 mbyte 4k 2 256 mbyte 4k 16m x 16 1 13 9 i_ad[26] i_ad[25] 64 mbyte 2k 2 128 mbyte 2k notes: 1. table indicates 32-bit-wide memory subsystem sizes 2. table indicates 32-bit-wide memory page sizes
functional overview august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 26 document number: 306261-003 the memory controller is a 32-bit only interface. if a x1 6 memory chip is used, a minimum of two memory chips would be required to facilitate the 32 -bit interface required by the ixp45x/ixp46x network processors. if ecc is required, additional memories would need to be added. for more information on ddri sdram support and configuration see the intel ? ixp45x and intel ? ixp46x product line of networ k processors developer?s manual . the memory controller interna lly interfaces to the north ahb, south ahb, and memory port interface with independent inte rfaces. this architecture allows ddri sdram transfers to be interleaved and pipelined to achie ve maximum possible efficiency. the maximum burst size supported to the ddri sdram interface is eight 32-bit words. this burst size allows the best efficiency/fairness perfor mance between peripheral accesses from the north ahb, the south ahb, and the mpi. the programming priority of the mcu is for the memory port in terface to have the highest priority and two ahb ports will have the next highest priority. for more information on mcu arbitration support and configuration see the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual . one item to be aware of is that when ecc is being used, the memo ry chip chosen to support the ecc must match that of the technology chosen on the interface. therefore, if x8 in a given configuration technology is chosen then the ecc memory chip must be the same. if a x16 configuration is chosen then a x16 ch ip must be used for the ecc chip. 3.1.9 expansion interface the expansion interface allows eas y and ? in most cases ? glue-l ess connection to peripheral devices. it also provides input information for device configuration after reset. some of the peripheral device types are sram, fl ash, atm control interf aces, and dsps used for voice applications. (some voice configurations can be supported by the hss interfaces and the intel xscale core, implementing voice-compression algorithms.) the expansion interface function s in two modes of operation: 512 mbit 64m x 8 1 13 11 i_ad[28] i_ad[27] 256 mbyte 8k 2 512 mbyte 8k 32m x 16 1 13 10 i_ad[27] i_ad[26] 128 mbyte 4k 2 256 mbyte 4k 1 gbit 128m x 8 1 14 11 i_ad[29] i_ad[28] 512 mbyte 8k 21 gbyte8k 64m x 16 1 14 10 i_ad[28] i_ad[27] 256 mbyte 4k 2 512 mbyte 4k table 4. supported ddri memory configurations (sheet 2 of 2) ddri sdram technology ddri sdram arrangement # banks address size leaf select total memory size 1 page size 2 row col ddri_ba[1] ddri_ba[0] notes: 1. table indicates 32-bit-wi de memory subsystem sizes 2. table indicates 32-bit-wide memory page sizes
functional overview intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 27 ? legacy (16-bit, data mode) ? enhanced (32-bit, data mode) 3.1.9.1 expansion bus legacy mode of operation in the legacy mode of operation, the expansion interface is a 16-bit interface that allows an address range of 512 bytes to 16 mbytes, using 24 address lines for each of the eight independent chip selects. accesses to the expansion bus interface is completed in five phases. each of the five phases can be lengthened or shortened by setting various configurat ion registers on a per-chip-select basis. this feature allows the ixp45x/ixp46x network processors to connect to a wide variety of peripheral devices with varying speeds. the expansion interface supports intel or motorola* microproces sor-style bus cycles. the bus cycles can be configured to be multiplexed address/ data cycles or separate address/data cycles for each of the eight chip-selects. additionally, chip selects 4 through 7 can be conf igured to support texas instruments* hpi-8 or hpi-16 style accesses for dsps. the expansion interface is an as ynchronous interface to externally connected chips. however, a clock must be supplied to expansion interface of the ixp45x/ixp46x netw ork processors for the interface to operate. this clock can be driven fr om gpio 15 or an extern al source. the maximum clock rate that the expansion interface can accept in legacy mode of operation is 66 mhz. if gpio 15 is used as the clock source, the expansion bu s interface can only be clocked at a maximum of 33.32 mhz. gpio 15?s maximum clock rate is 33.32 mhz. by providing this legacy mode of operation, co de developed for previous generations of this platform becomes easily portable. 3.1.9.2 expansion bus enhanced mode of operation in the enhanced mode of operat ion, the expansion interface is a 32-bit interface that allows an address range of 512 bytes to 32 mbytes per chip select on ixp45x/ixp46x network processors, using 25 address lines for each of th e eight independent chip selects. additionally, in enhanced mode, the interface supports shared access to the bus with external masters. this shared access is achie ved with four request/ grant pins and an integrated arbiter. not only can external devices access each other, but they can also access the ixp45x/ixp46x network processors? internal registers (i ncluding the ddri sdram interface). the advantage to this feature is that shared memory access can be achieved by using the ddri sdram interface attached to ix p45x/ixp46x network processors . this lowers the system?s overall bill of materials. enhanced mode also supports synchronous transfer s at speeds of up to 80 mhz with a 40-pf load. in addition to fully synchronous support, the enhanced mode also supports burst transfers of up to eight-word lengths. the synchronous bus support is compatible to zero bus turnaround (zbt) sram cycles for inbound/outbound transactions for both read/write transactions. additionally, the outbound read transactions can support the intel strataflash ? k3 synchronous- burst support.
functional overview august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 28 document number: 306261-003 byte-wide parity is an optional configuration of this interface in all m odes of operation except: ? intel strataflash ? k3 synchronous-burst mode ? hpi mode at the de-assertion of reset, the 25-bit address bu s is used to capture co nfiguration information from the levels that are applied to the pins at this time. external pull-up/pull-down resistors are used to tie the signals to particular logic levels. (for additional details, see ?package information? on page 40 .) if a signal is required to be placed into a pull-up state during this initialization period, the ixp45x/ixp46x network processors contain internal weak pull-ups. depending upon the system design, pull-down resistors may be the only thing required. 3.1.10 high-speed, serial interfaces the high-speed, serial interfaces (hss) are six-signal interfaces that support serial transfer speeds from 512 khz to 8.192 mhz, for some models of the ixp45x/ixp46x network processors. (for processor-specific speeds, see table 3 on page 19 .) each interface allows direct connection of up to four t1/e1 framers and codec/slics to the ixp45x/ixp46x network processors . the high-speed, serial interfaces are capable of supporting various protocols, based on the implementation of the code developed for the network processor engine core. for a list of supported protocols, see the intel ? ixp400 software programmer?s guide . 3.1.11 uarts the uart interfaces are a 16550-compliant uart wi th the exception of transmit and receive buffers. transmit and receive buffers are 64 by tes-deep versus the 16 bytes required by the 16550 uart specification. the interfaces can be configured to support sp eeds from 1,200 baud to 921 kbaud. the interfaces support configurations of: ? five, six, seven, or eight data-bit transfers ? one or two stop bits ? even, odd, or no parity the request-to-send (rts_n) and clear-to-send (c ts_n) modem control signals also are available with the interface for hardware flow control. 3.1.12 gpio there are 16 gpio pins supported by the ixp 45x/ixp46x network processors. gpio pins 0 through 13 can be configured to be general-purp ose input or general-purpose output. additionally, gpio pins 0 through 12 can be configured to be an interrupt input. gpio pin 14 can be configured similar to gpio pin 13 or as a clock output. the output-clock configuration can be set at various speeds, up to 33 mhz, with various duty cycles. gpio pin 14 is configured as an input, upon reset.
functional overview intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 29 gpio pin 15 can be configured the same as gp io pin 13 or as a clock output. the output-clock configuration can be set at various speeds, up to 33 mhz, with various duty cycles. gpio pin 15 is configured as an output, upon reset. gpio pin 15 can be used to clock the expansion interface, after reset. several other gpio pins can serve as an alternate functio n, as outlined in table 5 . 3.1.13 internal bus performance monitoring unit (ibpmu) the ixp45x/ixp46x network processors contain a performance monitoring unit that may be used to capture predefined events with in the system outside of the inte l xscale core. these features aid in measuring and monitoring various system parameters that contribute to the overall performance of the processor. the performance monitoring (pm on) facility provided comprises: ? eight programmable event counters (pecx) ? previous master/slave register ? event selection multiplexor the programmable event counters are 27 bits wide. each counter may be programmed to observe one event from a defined set of events. an event cons ists of a set of parameters which define a start condition and a stop condition. the monitored events are sel ected by programming the ev ent select registers (esr). 3.1.14 interrupt controller the ixp45x/ixp46x network processors implemen t up to 64 interrupt sources to allow an extension of the intel xscale core?s fiq and ir q interrupt sources. these sources can originate from some external gpio pins, internal peripheral interfaces, or internal logic. table 5. gpio alternate function table gpio pin number alternate function 0 external usb 1.1 device clock 1 external usb 2.0 host clock 2 npe a external condition 0 3 npe a external condition 1 4 npe b external condition 4 5 npe b external condition 5 6 npe c external condition 2 7 auxiliary ieee1588 master snapshot 8 auxiliary ieee1588 slave snapshot 9:13 (reserved) 14 output clock 14 15 output clock 15
functional overview august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 30 document number: 306261-003 the interrupt controller can configure each interr upt source as an fiq, irq, or disabled. the interrupt sources tied to interrupt 0 to 7 can be prioritized. the remaining interrupts are prioritized in ascending order. for example, interrupt 8 has a higher priority than 9, 9 has a higher priority than 10, and 30 has a higher priority that 31. an additional level of priority can be set for inte rrupts 32 through 64. this priority setting gives any interrupt between 32 through 64 priority over interrupts 0 through 31. 3.1.15 timers the ixp45x/ixp46x network proces sors contain four internal ti mers operating at 66.667 mhz (which is 2* osc_in input pin) to allow task scheduling and prevent software lock-ups. the device has four 32-bit counters: the timestamp timer and the two general-purpose timers have the optional ability to use a pre- scaled clock. a programmable pre-scaler can be us ed to divide the input clock by a 16-bit value. the input clock can be either the apb clock (6 6.66 mhz) or a 20-ns version of the apb clock (50 mhz). by default all timers use the apb clock. the 16-bit pre-scale value ranges from divide by 2 to 65,536 and results in a new clock enable available for the timers that ranges from 33.33 mhz down to 1,017.26 hz. the timestamp timer also contains a 32-bit compare register that allows an interrupt to be created at times other than time 0. 3.1.16 ieee 1588 hardware assistance in a distributed control system containing multiple clocks, individual clocks tend to drift apart. some kind of correction mechanism is necessary to synchronize the individual clocks to maintain global time, which is accurate to some clock re solution. the ieee 1588 standard for a precision clock synchronization protocol for networked meas urement and control systems can be used for this purpose. the ieee 1588 standard defines several messages that can be used to exchange timing information. the ixp45x/ixp46x network processors implement the ieee 1588 hardware-assist logic on three of the mii interfaces. using the hardware assist logic along with softwa re running on the intel xscale core, a full source or sink capable ieee-1588 compliant network node can be implemented. note: the ixp455 network processor does not support ieee 1588 hardware-assist. 3.1.17 synchronous seri al port interface the ixp45x/ixp46x network pro cessors have a dedicated synchronous serial port (ssp) interface. the ssp interface is a fu ll-duplex synchronous seri al interface. it can connect to a variety of external analog-to-digita l (a/d) converters, audio and telecom codecs, and many other devices which use serial protocols for transferring data. it supports national?s microwire*, texas instrume nts?* synchronous serial protocol (ssp), and motorola's* serial peripheral interface (spi*) protocol. ? watch-dog timer ? timestamp timer ? two general-purpose timers
functional overview intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 31 the ssp operates in master mode (the attached peripheral functions as a slave), and supports serial bit rates from 7.2 kbps to 1.8432 mbps using th e on-chip, 3.6864-mhz clock, and bit rates from 65.10 kbps to 16.67 mbps using a maximum off-chip, 33.33 mhz clock. serial data formats may range from 4 to 16 bits in length. two on-chip re gister blocks function as independent fifos for data, one for each direction. the fifos are 16 entries deep x 16 bi ts wide. each 32-bit word from the system fills one entry in a fifo using the lower half 16-bits of a 32-bit word. 3.1.18 i 2 c interface the i 2 c bus interface unit allows the ixp45x/ixp46x network processo rs to serve as a master and slave device residing on the i 2 c bus. the i 2 c bus is a two-pin serial bus. sda is the data pin for input and output functions and scl is the clock pin for reference and control of the i 2 c bus. the i 2 c bus allows the ixp45x/ixp46x networ k processors to interface to other i 2 c peripherals and micro-controllers for system management f unctions. the serial bus requires a minimum of hardware for an economical system to relay status and reliability information on the ixp45x/ ixp46x network processors subsystem to an external device. the i 2 c bus interface unit is a peripheral device that resides on the ix p45x/ixp46x network processors? apb. data is transm itted to and received from the i 2 c bus via a buffered interface. control and status information is relayed through a set of memory-mapped registers. refer to the i 2 c bus specification for complete details on i 2 c bus operation. the i 2 c supports: ? multi-master capabilities ? slave capabilities the i 2 c unit supports both fast-mode operation ? at 400 kbps ? and standard mode ? at 100 kbps. fast mode logic levels, formats, capacitive loading and protocols function the same in both modes. the i 2 c unit does not support i 2 c 10-bit addressing or cbus. 3.1.19 aes/des/sha/md-5 the ixp45x/ixp46x network pro cessors implement on-chip hard ware acceleration for underlying security and authentication algorithms. the encryption/decryption algorithms supported ar e aes, single pass aes-ccm, des, and triple des. these algorithms are co mmonly found when implementing ipsec, vpn, wep, wep2, wpa, and wpa2. the authentication algorithms supported are md-5, sha-1, sha-256, sha-384, and sha-512. inclusion of sha-384 and sha-512 allows 256-bit ke y authentication to pair up with 256-bit aes support. 3.1.20 cryptography unit the cryptography unit implements three major functions: ? exponentiation unit (eau) ? random number generator (rng) ? secure hash algorithm (s ha function for the rng)
functional overview august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 32 document number: 306261-003 the eau supports various large number arithmetic operations. these operations include modular exponentiation, modular reduction, multiply, ad d and subtract. these ope rations are controlled through a set of memory mapped registers. paramete rs for and results of the operations are written in little-endian ordering into a ram (contained within the eau) which the eau state machine accesses and also uses for temporary registers. th e arithmetic operations supported by the eau are used by software executing in th e host processor to build larger cryptographic functions such as signing and verification procedur es. since the eau executes only on e operation at a time, the host processor must serialize the requ ired operations to the eau. the eau begins operating after the host processor has moved data into the eau ram and loads the eau?s command register with an appropriate command. af ter executing the command, the eau appropriately sets its status bits and waits idle until it receives another command from the host processor. the rng unit provides a digital, random-number generation capability. it uses a lfsr (linear feedback shift register) to generate a sequen ce of pseudo-random bits . these sequences are shifted into a fifo of 32-bit words, which may be read sequentially from the random number register. a new word is generated every 32 clocks and the rng will buffer 16 of these words at a time. the output of the rng should be passed through the sha engine for added randomness. the host processor (intel xscale core) is responsible for implementing this sha-based, random-number generation. the lfsr also allows one entropy so urce. the entropy source is fed in from a pn sequence generator which has a period of 2^42 - 1. the coefficients for the pn sequence is chosen such that it produces the maximal sequence length. the coefficients are not mentioned for security reasons. the coefficients for th e 128-stage lsfr are similarly not mentioned here for security reasons. 3.1.21 queue manager the queue manager provides a means for maintaining coherency for data handling between various processors cores contained on the ixp4 5x/ixp46x network proces sors (npe to npe, npe to intel xscale core, etc.). it maintains the qu eues as circular buffers in an embedded 8-kbyte sram. the queue manager also implements the stat us flags and pointers required for each queue. the queue manager manages 64 independent queues. each queue is configurable for buffer and entry size. additionally status flags are maintained for each queue. the queue manager interfaces include an advan ced high-performance bus (ahb) interface to the npes and intel xscale core (or any other ahb bus master), a flag bus interface, an event bus (to the npe condition select logic), and two interrupts to the intel xscale core. the ahb interface is used for configuration of the queue manager and provides access to queues, queue status, and sram. individual queue status for queues 0-31 is communicated to the npes via the flag bus. combined queue status for queues 32-63 are communicated to the npes via the event bus. the two interrupts, one for queues 0-31 and one for queues 32-63, provide status interrupts to the intel xscale core.
functional overview intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 33 3.2 intel xscale ? core the intel xscale technology is compliant with the intel ? strongarm * version 5te instruction-set architecture (isa). the in tel xscale core, shown in figure 4 , is designed with intel, 0.18-micron production semiconductor process technology. this process technology ? with the compactness of the intel ? strongarm * risc isa ? enables the intel xscale core to operate over a wide speed and power range, producing industry-leading mw/mips performance. intel xscale core features include: ? seven/eight-stage super-pipeline promotes high-speed, efficient core performance ? 128-entry branch target buffer keeps pipeline fi lled with statistically correct branch choices ? 32-entry instruction memory-man agement unit for logical-to-ph ysical address translation, access permissions, and instruc tion-cache (i-cache) attributes ? 32-entry data-memory management unit for logi cal-to-physical address translation, access permissions, data-cach e (d-cache) attributes ? 32-kbyte instruction cache can hold entire progr ams, preventing core st alls caused by multi- cycle memory accesses ? 32-kbyte data cache reduces core stalls caused by multi-cycle memory accesses ? 2-kbyte mini-data cache fo r frequently changing data streams avoids ?thrashing? of the d- cache ? four-entry, fill-and-pend buffers to promote core efficiency by al lowing ?hit-under-miss? operation with data caches ? eight-entry write buffer allows the core to cont inue execution while data is written to memory ? multiple-accumulate coprocessor that can do two simultaneous, 16 -bit, simd multiplies with 40-bit accumulation for efficient, hi gh-quality media an d signal processing ? performance monitoring unit (pmu) furnishing two 32-bit event counters and one 32-bit cycle counter for analysis of hit rates, etc. this pmu is for the intel xscale core only. an additional pmu is supplied for monitoring of internal bus performance. ? jtag debug unit that uses hardware break point s and 256-entry trace history buffer (for flow- change messages) to debug programs
functional overview august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 34 document number: 306261-003 3.2.1 super pipeline the super pipeline is composed of integer, multiply-accumula te (mac), and memory pipes. the integer pipe has seven stages: ? branch target buffer (btb)/fetch 1 ? fetch 2 ? decode ? register file/shift ? alu execute ? state execute ? integer writeback the memory pipe has eight stages: ? the first five stages of the integer pipe (btb/fetch 1 through alu execute) . . . then finishes with the following memory stages ? data cache 1 ? data cache 2 ? data cache writeback figure 4. intel xscale ? core block diagram a9568-01 multiply accumulate execution core interrupt request instruction fiq coprocessor interface irq data address data system management debug/ pmu jtag south ahb bus data cache 32 kb mini-data cache 2 kb m m u instruction cache 32 kb m m u branch target cache
functional overview intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 35 the mac pipe has six to nine stages: ? the first four stages of the integer pipe (btb/fetch 1 through register file/ shift) . . . then finishes with the following mac stages ? mac 1 ? mac 2 ? mac 3 ? mac 4 ? data cache writeback the mac pipe supports a data-dependent early terminate where stages mac 2, mac 3, and/or mac 4 are bypassed. deep pipes promote high instruct ion execution rates only when a means exists to successfully predict the outcome of branch in structions. the branch target buffer provides such a means. 3.2.2 branch target buffer each entry of the 128-entry branch target bu ffer (btb) contains the address of a branch instruction, the target address associated with the branch instruction, and a previous history of the branch being taken or not taken. the history is recorded as one of four states: the btb can be enabled or disabled via coprocessor 15, register 1. when the address of the branch in struction hits in the btb and its history is strongly or weakly taken, the instruction at the branch target address is fetched. when its history is strongly or weakly not-taken, the next sequential instruction is fe tched. in either case the history is updated. data associated with a branch instruction enters the btb the first time the branch is taken. this data enters the btb in a slot with a history of strongly not-taken (overwriting previous data when present). successfully predicted branches avoid any branch-latency pena lties in the super pipeline. unsuccessfully predicted branches result in a four-to-five-cycle, branch-latency penalty in the super pipeline. 3.2.3 instruction memo ry management unit for instruction pre-fetches, the instruction memory management unit (immu) controls logical-to- physical address translation, memory access pe rmissions, memory-domain identifications, and attributes (governing operation of the instruction cache). the immu contains a 32-entry, fully associative instruction-translat ion, look-aside buffer (itlb) that has a round-robin replacement policy. it lb entries zero through 30 can be locked. when an instruction pre-fetch misses in the it lb, the immu invokes an automatic table-walk mechanism that fetches an associated descriptor from memory and loads it into the itlb. the descriptor contains in formation for logical-to -physical address tran slation, memory-access permissions, memory-domain iden tifications, and attri butes governing operat ion of the i-cache. ? strongly taken ? weakly taken ? weakly not taken ? strongly not taken
functional overview august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 36 document number: 306261-003 the immu then continues the inst ruction pre-fetch by using the ad dress translation just entered into the itlb. when an instruction pre-fetch hits in the itlb, the immu continues the pre-fetch using the address translation al ready resident in the itlb. access permissions for each of up to 16 memo ry domains can be programmed. when an instruction pre-fetch is attempted to an area of memory in violation of access permissions, the attempt is aborted and a pre-fetch abort is sent to the core for exception processing. the immu and dmmu can be enabled or disabled together. 3.2.4 data memory management unit for data fetches, the data memory management unit (dmmu) controls logical-to-physical address translation, me mory-access permissions, memory-domai n identifications, and attributes (governing operation of the data cache or mini-data cache and writ e buffer). the dmmu contains a 32-entry, fully associative data-translation, look-aside buffer (dtlb) that has a round-robin replacement policy. dtlb entries 0 through 30 can be locked. when a data fetch misses in the dtlb, the dmmu invokes an automatic table-walk mechanism that fetches an associated desc riptor from memory and loads it into the dtlb. the descriptor contains information fo r logical-to-physical ad dress translation, memo ry-access permissions, memory-domain identifications, a nd attributes (governing operat ion of the d-cach e or mini-data cache and write buffer). the dmmu continues the data fetch by using the address translation just entered into the dtlb. when a data fetch hits in the dtlb, the dmmu continues the fetch using the address translation already resident in the dtlb. access permissions for each of up to 16 memory domains can be programmed. when a data fetch is attempted to an area of memory in violation of access permission s, the attempt is aborted and a data abort is sent to the core for exception processing. the immu and dmmu can be enabled or disabled together. 3.2.5 instruction cache the instruction cache (i-cache) can contain high-use, multiple-code segments or entire programs, allowing the core access to instructions at core fr equencies. this prevents core stalls caused by multi-cycle accesses to external memory. the 32-kbyte i-cache is 32-set/32 -way associative, where each set contains 32 ways and each way contains a tag address, a cache line of instructions (eight 32-bit wo rds and one parity bit per word), and a line-valid bit. for each of the 32 sets, 0 through 28 ways can be locked. unlocked ways are replaceable via a round-robin policy. the i-cache can be enabled or disa bled. attribute bi ts within the descriptors ? contained in the itlb of the immu ? provide some control over an enabled i-cache. when a needed line (eight 32-bit wo rds) is not present in the i-cache, the line is fetched (critical word first) from memory via a two-level, deep -fetch queue. the fetch queue allows the next instruction to be accessed from the i-cache, but onl y when its data operands do not depend on the execution results of the instruction being fetched via the queue.
functional overview intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 37 3.2.6 data cache the data cache (d-cache) can contai n high-use data such as lookup tables and filter coefficients, allowing the core access to data at core frequencie s. this prevents core st alls caused by multi-cycle accesses to external memory. the 32-kbyte d-cache is 32-set/ 32-way associative, where each set contains 32 ways and each way contains a tag address, a cach e line (32 bytes with one parity bit per byte) of data, two dirty bits (one for each of two eight-byte groupings in a line), and on e valid bit. for each of the 32 sets, zero through 28 ways can be locked, unlocked, or used as local sram. unlocked ways are replaceable via a round-robin policy. the d-cache (together with the mini -data cache) can be enabled or di sabled. attribute bits within the descriptors, contained in the dtlb of the dmmu, provide significant control over an enabled d-cache. these bits speci fy cache operating modes such as read and writ e allocate, write-back, write-through, and d-cache vers us mini-data cache targeting. the d-cache (and mini-data cache) work with the load buffer a nd pend buffer to provide ?hit- under-miss? capability that allows the core to acce ss other data in the cache after a ?miss? is encountered. the d-cache (and mini-data cache) work s in conjunctio n with the write buffer for data that is to be stored to memory. 3.2.7 mini-data cache the mini-data cache can contain freq uently changing data streams su ch as mpeg video, allowing the core access to data streams at core frequencies. this prevents core st alls caused by multi-cycle accesses to external memory. the mini-data cache relieves the d-cac he of data ?thrashing? caused by frequently changing data streams. the 2-kbyte, mini-data cache is 32-set/two-way asso ciative, where each set contains two ways and each way contains a tag address, a cache line (32 bytes with one parity b it per byte) of data, two dirty bits (one for each of two ei ght-byte groupings in a line), an d a valid bit. the mini-data cache uses a round-robin replacement policy, and cannot be locked. the mini-data cache (together with the d-cache) can be enabled or disabled. attribute bits contained within a coprocessor register specify op erating modes write and/or read allocate, write- back, and write-through. the mini-data cache (and d- cache) work with the load buffer and pend buffer to provide ?hit- under-miss? capability that allows the core to acce ss other data in the cache after a ?miss? is encountered. the mini-data cache (and d-cache) wo rks in conjunc tion with the write buffer for data that is to be stored to memory. 3.2.8 fill buffer and pend buffer the four-entry fill buffer (fb) works with the core to hold non-cacheable loads until the bus controller can act on them. the fb and the four-entry pend buffer (pb) work with the d-cache and mini-data cache to provide ?hit-under-miss? capability, allowing the core to seek other data in the caches while ?miss? data is being fetched from memory.
functional overview august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 38 document number: 306261-003 the fb can contain up to four uniq ue ?miss? addresses (logical), allo wing four ?misses? before the core is stalled. the pb holds up to four a ddresses (logical) for additio nal ?misses? to those addresses that are already in the fb. a coprocessor register can speci fy draining of the fill and pend (write) buffers. 3.2.9 write buffer the write buffer (wb) holds data for storage to me mory until the bus controll er can act on it. the wb is eight entries deep, where each entry holds 16 bytes. the wb is constantly enabled and accepts data from the core, d-cache, or mini-data cache. coprocessor 15, register 1 specifies whether wb coalescing is enabled or disabled. when coalescing is disabled, stores to memory occur in program order ? regardless of the attribute bits within the descriptors located in the dtlb. when coalescing is enabled, the attribute bits within the descriptors lo cated in the dtlb are examined to determine when coalescing is enable d for the destination region of memory. when coalescing is enabled in both cp15, r1 and the d tlb, data entering the wb can coalesce with any of the eight entries (16 bytes) and be stored to th e destination memory region, but possibly out of program order. stores to a memory region speci fied to be non-cacheable and non- bufferable by the attribute bits within the descriptors located in the dtlb causes the core to stall until the store completes. a coprocessor register can specify draining of the write buffer. 3.2.10 multiply-accumulate coprocessor for efficient processing of high-quality, media- and-signal-processing al gorithms, the multiply- accumulate coprocessor (cp0) provides 40-bit accumulation of 16 x 16, dual-16 x 16 (simd), and 32 x 32 signed multiplies. speci al mar and mra instructions are implemented to move the 40-bit accumulator to two core-gener al registers (mar) and move two core-general registers to the 40-bit accumulator (mra). the 40-bit accumulator can be stored or loaded to or from d-cache, mini-data cache, or memory usin g two stc or ldc instructions. the 16 x 16 signed multiply-accumula tes (miaxy) multiply either the high/high, low/low, high/ low, or low/high 16 bits of a 32-bit core genera l register (multiplier) and another 32-bit core general register (multiplicand) to produce a full, 32-bit product that is sign-extended to 40 bits and added to the 40-bit accumulator. dual-signed, 16 x 16 (simd) multiply-accumulates (miaph) multiply the high/high and low/low 16-bits of a packed 32-bit, core -general register (multiplier) and another packed 32-bit, core- general register (multiplicand) to produce two 16-bits products that are both sign-extended to 40 bits and added to the 40-bit accumulator. the 32 x 32 signed multiply-accumu lates (mia) multiply a 32-b it, core-general register (multiplier) and another 32-bit, core-general re gister (multiplicand) to produce a 64-bit product where the 40 lsbs are added to the 40-bit accu mulator. the 16 x 32 versions of the 32 x 32 multiply-accumulate instructions complete in a single cycle.
functional overview intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 39 3.2.11 performance monitoring unit the performance monitoring unit (pmu) contains f our 32-bit, event counters and one 32-bit, clock counter. the event counters can be programmed to monitor i-cache hit rate, data caches hit rate, itlb hit rate, dtlb hit rate, pipeline stalls, btb prediction hit rate, and instruction execution count. 3.2.12 debug unit the debug unit is accessed through the jtag port. the industry-standard, ieee 1149.1 jtag port consists of a test access port (tap) controller, boundary-scan register, instruction and data registers, and dedicated signals tdi, tdo, tck, tms, and trst#. the debug unit ? when used with debugger application code running on a host system outside of the intel xscale core ? allows a program, running on the intel xscale core, to be debugged. it allows the debugger application code or a debug exception to stop program execution and redirect execution to a debug-handling routine. debug exceptions are instruction breakpoint, data breakpoint, software breakpoint, external debug breakpoint, exception vector trap, and trace buffer full breakpoint. once execution has stopped, the debugger application code can exam ine or modify the core?s state, coprocessor state, or memory. the debugger application code can then restart program execution. the debug unit has two hardware-ins truction, break point registers; two hardware, data-breakpoint registers; and a hardware, data-breakpoint control register. the second data-breakpoint register can be alternatively used as a mask register for the first data-breakpoint register. a 256-entry trace buffer provides the ability to capture control flow messages or addresses. a jtag instruction (ldic) can be us ed to download a debug handler via the jtag port to the mini- instruction cache (the i-cache has a 2-kbyte, mini-instruction cache, like the mini-data cache, that is used only to hold a debug handler).
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 40 document number: 306261-003 4.0 package information this section contains information on the following topics: ? ?package description? which includes ?package drawings? , ?package markings? , and ?part numbers? ? ?functional signal definitions? on page 46 ? ?signal-pin descriptions? on page 89 ? ?package thermal specifications? on page 114 4.1 package description the ixp45x/ixp46x network processors are built us ing a 544-ball, plastic ball grid array (pbga) package with a drop-in heat spreader (h). for all extended temperature products and the 667-mhz speed option of the commercial temperature product, a 10-mm-high, thermal-adhesive-based heat si nk will be required. the heat sink does not force the addition of any surface area to the board design. 4.1.1 package drawings the package is shown in figure 5 and figure 6 .
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 41 figure 5. 544-pin lead pbga package ? first of two drawings 0.75 1.17 1.27 0.61 b3846-01
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 42 document number: 306261-003 figure 6. 544-pin lead pbga package ? second of two drawings b3847-01
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 43 4.1.2 package markings figure 7. package markings: intel ? ixp45x and intel ? ixp46x product line of network processors? extended and commercial temperature, lead -free / compliant with standard for restriction on the use of hazardous substances (rohs) notes: 1. part number field ? for the different part numbers of intel ? ixp45x and intel ? ixp46x product line of network processors, see section 4.1.3 . 2. package ball counts ? intel ? ixp45x and intel ? ixp46x product line of network pr ocessors have a ball count of 544. 3. drawing is not to scale. ma rking content is an example. part number finish site traceability code intel copyright assembly site traceability code pin # 1 ewixp465aet fpo# '04 atpo# yww korea i m c e1 lead-free designator (e1) drop-in heat spreader (24-mm diameter) b4916-001 assembly year (y) and work week (ww) and country of origin 1
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 44 document number: 306261-003 4.1.3 part numbers the tables in this section list the part numbers for the ixp46x product line of network processors ( table 6 and table 7 ) and the ixp45x product line of network processors ( table 8 and table 9 ). figure 8. package markings: intel ? ixp45x and intel ? ixp46x product line of network processors ? commercial and extended temperature, lead-based notes: 1. part number field ? for the different part numbers of intel ? ixp45x and intel ? ixp46x product line of network processors, see section 4.1.3 . 2. package ball counts ? intel ? ixp45x and intel ? ixp46x product line of network processors have a ball count of 544. 3. drawing is not to scale. marking content is an example. part number finish site traceability code intel copyright assembly site traceability code pin # 1 gwixp465aet fpo# intel '04 atpo# yww korea i m c drop-in heat spreader (24-mm diameter) assembly year (y) and work week (ww) and country of origin b4923-001 1 table 6. intel ? ixp46x product line part numbers: lead (pb) packaging (sheet 1 of 2) device stepping speed (mhz) part number temperature offering ixp465 a1 667 gwixp465aae commercial ixp465 a1 533 gwixp465aad commercial ixp465 a1 400 gwixp465aac commercial ixp465 a1 266 gwixp465aab commercial ixp460 a1 667 gwixp460aae commercial ixp460 a1 533 gwixp460aad commercial ixp460 a1 400 gwixp460aac commercial
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 45 ixp460 a1 266 gwixp460aab commercial ixp465 a1 533 gwixp465aadt extended ixp465 a1 400 gwixp465aact extended ixp465 a1 266 gwixp465aabt extended ixp460 a1 533 gwixp460aadt extended ixp460 a1 400 gwixp460aact extended ixp460 a1 266 gwixp460aabt extended table 7. intel ? ixp46x product line part numbers: lead free (pb-free) packaging device stepping speed (mhz) part number temperature offering ixp465 a1 667 ewixp465aae commercial ixp465 a1 533 ewixp465aad commercial ixp465 a1 400 ewixp465aac commercial ixp465 a1 266 ewixp465aab commercial ixp460 a1 667 ewixp460aae commercial ixp460 a1 533 ewixp460aad commercial ixp460 a1 400 ewixp460aac commercial ixp460 a1 266 ewixp460aab commercial ixp465 a1 533 ewixp465aadt extended ixp465 a1 400 ewixp465aact extended ixp465 a1 266 ewixp465aabt extended ixp460 a1 533 ewixp460aadt extended ixp460 a1 400 ewixp460aact extended ixp460 a1 266 ewixp460aabt extended table 8. intel ? ixp45x product line part numbers: lead (pb) packaging device stepping speed (mhz) part number temperature offering ixp455 a1 533 gwixp455aad commercial ixp455 a1 400 GWIXP455AAC commercial ixp455 a1 266 gwixp455aab commercial ixp455 a1 533 gwixp455aadt extended ixp455 a1 400 GWIXP455AACt extended ixp455 a1 266 gwixp455aabt extended table 6. intel ? ixp46x product line part numbers: lead (pb) packaging (sheet 2 of 2) device stepping speed (mhz) part number temperature offering
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 46 document number: 306261-003 4.2 functional signal definitions the signal definition tables list pull-up and pull-down resistor recommendations when the particular enabled interface is not being used in the ap plication. these ex ternal resistor requirements are only needed if the particular model of ixp45x/ixp46x network processors has the particular interface enabled and the interface is not re quired in the application. warning: none of the ixp45x/ixp46x network proc essors? i/o pins are 5-v tolerant. disabled features within the ixp45x/ixp46x network processors do not require external resistors, as the processor will have internal pull-up or pull-down resistors enabled as part of the disabled interface. to determine which interfaces are no t enabled within the ixp45x/ixp46x network processors, see table 1 on page 14 . table 10 presents the legend for interpreting the type field in the other tables in this section of the document. table 9. intel ? ixp45x product line part numbers: lead free (pb-free) packaging device stepping speed (mhz) part number temperature offering ixp455 a1 533 ewixp455aad commercial ixp455 a1 400 ewixp455aac commercial ixp455 a1 266 ewixp455aab commercial ixp455 a1 533 ewixp455aadt extended ixp455 a1 400 ewixp455aact extended ixp455 a1 266 ewixp455aabt extended table 10. signal type definitions (sheet 1 of 2) symbol description i input pin only o output pin only i/o pin can be either an input or output od open drain pin pwr power pin gnd ground pin 1 driven to vcc 0 driven to vss x driven to unknown state id input is disabled h pulled up to vcc l pulled to vss pd pull-up disabled z output disabled
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 47 this section includes the following tables: ? table 11, ?ddr sdram interface? on page 48 ? table 12, ?pci controller? on page 50 ? table 13, ?high-speed, serial interface 0? on page 55 ? table 14, ?high-speed, serial interface 1? on page 57 ? table 15, ?utopia level 2/mii_a / smii[4] interface? on page 59 ? table 16, ?mii/smii interfaces? on page 68 ? table 17, ?expansion bu s interface? on page 76 ? table 18, ?uart interfaces? on page 79 ? table 19, ?serial peripheral port interface? on page 81 ? table 20, ?i2c interface? on page 82 ? table 21, ?usb host/device interfaces? on page 83 ? table 22, ?oscillator interface? on page 84 ? table 23, ?gpio interface? on page 85 ? table 24, ?jtag interface? on page 86 ? table 25, ?system interface? on page 86 ? table 26, ?power interface? on page 88 vo a valid output level is driven, allowed states -- 1, 0, h vb valid level on the signal, allowed states - 1, 0, h, z vi need to drive a valid input level, allowed states - 1, 0, h, z vod valid open drain output, allowed states are 0 or z pe pull-up enabled, equivalent to h tri output only/tristatable epu external 10k ohm pull-up is required on the board n/c no connect - pin must be connected as described table 10. signal type de finitions (sheet 2 of 2) symbol description
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 48 document number: 306261-003 table 11. ddr sdram interface (sheet 1 of 2) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description ddri_ck[2:0] z 0 vo vo o ddr sdram clock out ? provide the positive di fferential clocks to the external sdram memory subsystem. ddri_ck_n[2:0] z 1 vo vo o ddr sdram clock out ? provide the negative di fferential clocks to the external sdram memory subsystem. ddri_cs_n[1:0] z z vo vo o chip select ? must be asserted for a ll transactions to the ddr s dram device. one per bank. ddri_ras_n z z vo vo o row address strobe ? indicates that the current address on ddri_ma[13:0] is the row. ddri_cas_n z z vo vo o column address strobe ? indicates that the current address on ddri_ma[13:0] is the column. ddri_we_n z z vo vo o write strobe ? defines whether or not the current operation by the ddr sdram is to be a read or a write. ddri_dm[4:0] z z vo vo o data bus mask ? controls the ddr sdram data input buffers. asserting ddri_we_n causes the data on ddri_dq[31:0] and ddri_cb[7:0] to be written into the ddr sdram devices. ddri_dm[4:0] controls this operation on a per byte basis. ddri_dm[3:0] are intended to correspond to each byte of a word of data. ddri_dm[4] is intended to be utilized for the ecc byte of data. ddri_ba[1:0] z z vo vo o ddr sdram bank selects ? controls which of the internal ddr sdram banks to read or write. ddri_ba[1:0] are used for all technology types supported. ddri_ma[13:0] z z vo vo o address bits 13 through 0 ? indicates the row or column to access depending on the state of ddri_ras_n and ddri_cas_n. ddri_dq[31:0] z vb vb vb i/o data bus ? 32-bit wide data bus. ddri_cb[7:0] z vb vb vb i/o ecc bus ? eight-bit error correction code wh ich accompanies the data on ddri_dq[31:0]. when ecc is disabled and not being used in a sy stem design, these signals are not required for any connection. ddri_dqs[4:0] z vb vb vb i/o data strobes differential ? strobes that accompany the data to be read or written from the ddr sdram devices. data is sampled on the negative and positive edges of these strobes. ddri_dqs[3:0] are intended to correspond to each byte of a word of data. ddri_dqs4] is intended to be utilized for the ecc byte of data. note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 49 document number: 306261-003 ddri_cke[1:0] z b?00 vo vo o clock enables ? one clock after ddri_cke[1:0] is de-asserted, data is latched on dq[31:0] and ddri_cb[7:0]. burst counters within ddr sdram device are not incremented. de- asserting this signal places the ddr sdram in self-refresh mode. for normal operation, ddri_cke[1:0] must be asserted. ddri_rcvenout_n z 1 vo vo o receive enable out must be connected to ddri_rcvenin_n signal of the ixp45x/ ixp46x network processors and the propagation del ay of the trace length must be matched to the clock trace plus the average dq traces. ddri_rcvenin_n z vi vi vi i receive enable in provides delay informatio n for enabling the input receivers and must be connected to the ddri_rcvenout_n signal of the ixp45x/ixp46x network processors. ddri_rcomp tied off to a resistor tied off to a resistor tied off to a resistor tied off to a resistor o 20 ohm 1% tolerance resistor connected to ground used for process/temperature adjustments. ddri_vref vccm/ 2 vccm/2 vccm/2 vccm/2 i ddr sdram voltage reference ? is used to supply the reference voltage to the differential inputs of the memory controller pins. table 11. ddr sdram interface (sheet 2 of 2) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 50 document number: 306261-003 table 12. pci controller (sheet 1 of 5) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description pci_ad[31:0] z z vb vb i/o pci address/data bus used to transfer address and bidirectional data to and from multiple pci devices. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the pci soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a syst em design, this interface/ signal is not required for any connection. pci_cbe_n[3:0] z z vb vb i/o pci command/byte enables is used as a command word during pci address cycles and as byte enables for data cycles. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the pci soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a syst em design, this interface/ signal is not required for any connection. pci_par z z vb vb i/o pci parity used to check parity across the 32 bi ts of pci_ad and the four bits of pci_cbe_n. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the pci soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a syst em design, this interface/ signal is not required for any connection. pci_frame_n z z vb vb i/o pci cycle frame used to signify the beginning and duration of a transaction. the signal will be inactive prior to or during the final data phase of a given transaction. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the pci soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a syst em design, this interface/ signal is not required for any connection. note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 51 document number: 306261-003 pci_trdy_n z z vb vb i/o pci target ready informs that the target of the pci bus is ready to complete the current data phase of a given transaction. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the pci soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a syst em design, this interface/ signal is not required for any connection. pci_irdy_n z z vb vb i/o pci initiator ready informs the pci bus that the initiator is ready to complete the transaction. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the pci soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a syst em design, this interface/ signal is not required for any connection. pci_stop_n z z vb vb i/o pci stop indicates that the current target is requesting the current initiator to stop the current transaction. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the pci soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a syst em design, this interface/ signal is not required for any connection. pci_perr_n z z vb vb i/o pci parity error asserted when a pci parity error is detected ? between the pci_par and associated information on the pci_ad bus and pci_cbe_n ? during all pci transactions, except for special cycles. the agent receiving data will drive this signal. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the pci soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a syst em design, this interface/ signal is not required for any connection. table 12. pci controller (sheet 2 of 5) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 52 document number: 306261-003 pci_serr_n z z vb vb i/od pci system error asserted when a parity error occurs on special cycles or any other error that will cause the pci bus not to function properly. this si gnal can function as an input or an open drain output. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the pci soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a syst em design, this interface/ signal is not required for any connection. pci_devsel_n z z vb vb i/o pci device select: ? when used as an output, pci_devsel_n indicates that device has decoded that address as the target of the requested transaction. ? when used as an input, pci_devsel_n indicates if any device on the pci bus exists with the given address. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the pci soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a syst em design, this interface/ signal is not required for any connection. pci_idsel z z vi vi i pci initialization device select is a chip select during configuration reads and writes. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the pci soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a syst em design, this interface/ signal is not required for any connection. pci_req_n[3:1] z z vi vi i pci arbitration request: used by the internal pci arbiter to allow an agent to request the pci bus. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the pci soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a syst em design, this interface/ signal is not required for any connection. table 12. pci controller (sheet 3 of 5) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 53 document number: 306261-003 pci_req_n[0] z z vi vi / vo i/o pci arbitration request: ? when configured as an input (pci arbiter enabled), t he internal pci arbiter will allow an agent to request the pci bus. ? when configured as an output (pci arbiter disabled) , the pin will be used to request access to the pci bus from an external arbiter. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the pci soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a syst em design, this interface/ signal is not required for any connection. pci_gnt_n[3:1] z z vo vo o pci arbitration grant: generated by the internal pci arbiter to allow an agent to claim control of the pci bus. pci_gnt_n[0] z z vo vi / vo i/o pci arbitration grant: ? when configured as an output (pci arbiter enabled) , the internal pci arbiter to allow an agent to claim control of the pci bus. ? when configured as an input (pci arbiter disabl ed), the pin will be used to claim access of the pci bus from an external arbiter. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the pci soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a syst em design, this interface/ signal is not required for any connection. table 12. pci controller (sheet 4 of 5) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 54 document number: 306261-003 pci_inta_n z z z vod o/d pci interrupt: used to request an interrupt. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the pci soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a syst em design, this interface/ signal is not required for any connection. pci_clkin z vi vi vi i pci clock: clock provides timing for all transactions on pci. all pci signals ? except inta#, intb#, intc#, and intd# ? are sampled on the rising edge of clk and timing parameters are defined with respect to this edge. the pci clock rate can operate at up to 66 mhz. when this interface/signal is enab led and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. table 12. pci controller (sheet 5 of 5) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 55 document number: 306261-003 table 13. high-speed, serial interface 0 (sheet 1 of 2) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description hss_txframe0 z z vb vb i/o the high-speed serial (hss) transmit frame signal ca n be configured as an input or an output to allow an external source become synchronized with the transmitted data. often known as a frame sync signal. configured as an input upon reset. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the hss soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interface/signal is not required for any connection. hss_txdata0 z z vod vod od transmit data out. open drain output. when this interface/signal is enabled and either us ed or unused in a system design, it should be pulled high with a 10-k ? resistor to v ccp . when this interface is disabled via the hss soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a sys tem design, this interface/ signal is not required for any connection. hss_txclk0 z z vb vb i/o the high-speed serial (hss) transmit clock signal can be configured as an input or an output. the clock can be a frequency ranging from 512 khz to 8.192 mhz. used to clock out the transmitted data. configured as an input upon reset. frame sync and data can be selected to be generated on the rising or falling edge of the transmit clock. when this inte rface/signal is enabled and is not being used in a system design, the interf ace/signal should be pulled high with a 10-k ? resistor. hss_rxframe0 z z vb vb i/o the high-speed serial (hss) receive frame signal can be configured as an input or an output to allow an external source to become synchronized with the received data. often known as a frame sync signal. configured as an input upon reset. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the hss soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interface/signal is not required for any connection. note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 56 document number: 306261-003 hss_rxdata0 z vi vi vi i receive data input. can be sampled on the risi ng or falling edge of the receive clock. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the hss soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interface/signal is not required for any connection. hss_rxclk0 z z vb vb i/o the high-speed serial (hss) receive clock signal c an be configured as an input or an output. the clock can be from 512 khz to 8.192 mhz. used to sample the received data. configured as an input upon reset. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. table 13. high-speed, serial interface 0 (sheet 2 of 2) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 57 document number: 306261-003 table 14. high-speed, serial interface 1 (sheet 1 of 2) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description hss_txframe1 z z vb vb i/o the high-speed serial (hss) transmit frame signal can be configured as an input or an output to allow an external source to be synchronized with the transmitte d data. often known as a frame sync signal. configured as an input upon reset. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the hss soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interface/signal is not required for any connection. hss_txdata1 z z vod vod od transmit data out. open drain output. when this interface/signal is enabled and either used or unused in a system design, it should be pulled high with a 10-k ? resistor to v ccp . when this interface is disabled via the hss soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interface/ signal is not required for any connection. hss_txclk1 z z vb vb i/o the high-speed serial (hss) transmit clock signal can be configured as an input or an output. the clock can be a frequency ranging from 512 khz to 8.192 mhz. used to clock out the transmitted data. configured as an input upon reset. frame sync and data can be selected to be generated on the rising or falling edge of the transmit clock. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. hss_rxframe1 z z vb vb i/o the high-speed serial (hss) receive frame signal can be configured as an input or an output to allow an external source to be synchronized with the received data. often known as a frame sync signal. configured as an input upon reset. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the hss soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interface/signal is not required for any connection. note: this table discusses all f eatures supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 58 document number: 306261-003 hss_rxdata1 z vi vi vi i receive data input. can be sampled on the risi ng or falling edge of the receive clock. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the hss soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interface/signal is not required for any connection. hss_rxclk1 z z vb vb i/o the high-speed serial (hss) receive clock signal can be configured as an input or an output. the clock can be from 512 khz to 8.192 mhz. used to sample the received data. configured as an input upon reset. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. table 14. high-speed, serial interface 1 (sheet 2 of 2) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all f eatures supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 59 document number: 306261-003 table 15. utopia level 2/mii_a/ sm ii[4] interface (sheet 1 of 9) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description utp_op_clk / etha_txclk zvi vi vii utopia mode of operation: utopia transmit clock input. also known as utp_tx_clk. this si gnal is used to synchronize all utopia transmit outputs to the rising edge of the utp_op_clk. mii mode of operation: externally supplied transmit clock. ? 25 mhz for 100 mbps operation ? 2.5 mhz for 10 mbps smii mode of operation: not used. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. utp_op_fco z z z vo tri utopia flow control output signal. also known as the txenb_n signal. used to inform the selected phy that data is being transmitted to the phy. placing the phy?s address on the utp_op_addr ? and bringing utp_ op_fco to logic 1, during the current clock ? followed by the utp_op_f co going to a logic 0, on the next clock cycle, selects which phy is active in mphy mode. in sphy configurations, utp_op_fco is used to in form the phy that the processor is ready to send data. this signal must be tied to vcc with an external 10-k ? resistor. utp_op_soc z z z vo tri start of cell. also known as tx_soc. active high signal is asserted when utp_op_data c ontains the first valid byte of a transmitted cell. this signal must be tied to vss with an external 10-k ? resistor. note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? for information on selecting the desired interface, see the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 60 document number: 306261-003 utp_op_data[3:0] / etha_txdata[3:0] zz z votri utopia mode of operation: utopia output data. also known as utp_tx_data. used to send data from the processor to an atm utopia level 2-compliant phy. mii mode of operation: transmit data bus to phy, asserted synchronous ly with respect to etha_txclk. this mac interface does not contain hardware hashing capabilities local to t he interface. in this mode of operation the pins represented by this interface are etha_txdata3:0]. smii mode of operation: not used. utp_op_data[4] / etha_txen zz z votri utopia mode of operation: utopia output data. also known as utp_tx_data. used to send data from the processor to an atm utopia level 2-compliant phy. mii mode of operation: indicates that the phy is being presented wi th nibbles on the mii interface. asserted synchronously, with respect to etha_txclk, at the first nibble of the preamble, and remains asserted until all the nibbles of a frame are presented. this mac does not contains hardware hashing capabilities local to the interface. smii mode of operation: not used. utp_op_data[6:5] z z z vo tri utopia mode of operation: utopia output data. also known as utp_tx_data. used to send data from the processor to an atm utopia level 2-compliant phy. table 15. utopia level 2/mii_a/ sm ii[4] interface (sheet 2 of 9) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? for information on selecting the desired interface, see the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 61 document number: 306261-003 utp_op_data[7] / smii_txdata[4] zz z votri utopia mode of operation: utopia output data. also known as utp_tx_data. used to send data from the processor to an atm utopia level 2-compliant phy. mii mode of operation: not used. smii mode of operation: output data for smii interface number four. the data on this signal is transmitted synchronously with respect to the rising edge of smii_clk when operating as an smii interface and synchronously with respect to the rising edge of smii_txclk when operating as a source synchronous smii interface utp_op_addr[4:0] z z z vo o transmit phy address bus. used by the processo r when operating in mphy mode to poll and select a single phy at any given time. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the utopia and/or the npe-a ethernet soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interf ace/signal is not required for any connection. utp_op_fci z vi vi vi i utopia output data flow control input: also known as the txfull/clav signal. used to inform the processor of the ability of eac h polled phy to receive a complete cell. for cell- level flow control in an mphy environment, txclav is an active high tri-st ateable signal from the mphy to atm layer. the utp_op_fci, which is c onnected to multiple mphy devices, will see logic high generated by the phy, one clock after t he given phy address is asserted ? when a full cell can be received by the phy. the utp_op_f ci will see a logic low generated by the phy one clock cycle, after the phy address is asserted ? if a full cell cannot be received by the phy. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the utopia and/or the npe-a ethernet soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interf ace/signal is not required for any connection. table 15. utopia level 2/mii_a/ sm ii[4] interface (sheet 3 of 9) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? for information on selecting the desired interface, see the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 62 document number: 306261-003 utp_ip_clk / etha_rxclk zvi vi vii utopia mode of operation: utopia receive clock input. also known as utp_rx_clk. this signal is used to synchr onize all utopia-rec eived inputs to the rising edge of the utp_ip_clk. mii mode of operation: externally supplied receive clock. ? 25 mhz for 100 mbps operation ? 2.5 mhz for 10 mbps this mac interface does not contain hardware hashing capabilities local to the interface. smii mode of operation: not used. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. utp_ip_fci z vi vi vi i utopia input data flow control input signal. also known as rxempty/clav. used to inform the processor of the ability of each polled phy to send a complete cell. for cell- level flow control in an mphy environment, rxclav is an active high tri-stateable signal from the mphy to atm layer. the utp_ip_fci, which is connected to multiple mphy devices, will see logic high generated by the phy, one clock after the given phy address is asserted, when a full cell can be received by the phy. the utp_ip_fci will see a logic low generated by the phy, one clock cycle after the phy address is asserted if a full cell cannot be received by the phy. in sphy mode, this signal is used to indicate to the processor that the phy has an octet or cell available to be transferred to the processor. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the utopia and/or the npe-a ethernet soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interf ace/signal is not required for any connection. table 15. utopia level 2/mii_a/ sm ii[4] interface (sheet 4 of 9) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? for information on selecting the desired interface, see the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 63 document number: 306261-003 utp_ip_soc z vi vi vi i start of cell. rx_soc active-high signal that is asserted when utp_ ip_data contains the first valid byte of a transmitted cell. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the utopia and/or the npe-a ethernet soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interf ace/signal is not required for any connection. utp_ip_data[3:0] / etha_rxdata[3:0] zvi vi vii utopia mode of operation: utopia input data. also known as rx_data. used by to the processor to receive data from an atm utopia level 2-compliant phy. mii mode of operation: receive data bus from the phy, asserted syn chronously with respect to etha_rxclk. smii mode of operation: not used. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the utopia and/or the npe-a ethernet soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interf ace/signal is not required for any connection. table 15. utopia level 2/mii_a/ sm ii[4] interface (sheet 5 of 9) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? for information on selecting the desired interface, see the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 64 document number: 306261-003 utp_ip_data[4] / etha_rxdv zvi vi vii utopia mode of operation: utopia input data. also known as rx_data. used by to the processor to receive data from an atm utopia level 2-compliant phy. mii mode of operation: receive data valid, used to inform the mii interface that the ethernet phy is sending data. this mac does not contains hardware hashi ng capabilities local to the interface. smii mode of operation: not used. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the utopia and/or the npe-a ethernet soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interf ace/signal is not required for any connection. table 15. utopia level 2/mii_a/ sm ii[4] interface (sheet 6 of 9) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? for information on selecting the desired interface, see the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 65 document number: 306261-003 utp_ip_data[5] / etha_col zvi vi vii utopia mode of operation: utopia input data. also known as rx_data. used by the processor to receive data fr om an atm utopia level 2-compliant phy. ? when npe a is configured in utopia mode of operation and the signal is not being used, it should be pulled high through a 10-k ? resistor. mii mode of operation: asserted by the phy when a coll ision is detected by the phy. ? when npe a is configured in mii mode of operat ion and the signal is not being used, it should be pulled low through a 10-k ? resistor. smii mode of operation: not used. ? when npe a is configured in smii mode of operat ion, this signal must be pulled high through a 10-k ? resistor. when this interface is disabled via the utopia and/ or the npe-a ethernet soft fuse (refer to the expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual ) and is not being used in a system design, this interface/ signal is not required for any connection. table 15. utopia level 2/mii_a/ sm ii[4] interface (sheet 7 of 9) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? for information on selecting the desired interface, see the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 66 document number: 306261-003 utp_ip_data[6] / etha_crs zvi vi vii utopia mode of operation: utopia input data. also known as rx_data. used by to the processor to receive data from an atm utopia level 2-compliant phy. mii mode of operation: asserted by the phy when the transmit medium or receive medium are active. de-asserted when both the transmit and receive medium are idle. remains asserted throughout the duration of collision condition. phy asserts crs asynchronously and de-asserts synchronously with respect to etha_rxclk. smii mode of operation: not used. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the utopia and/or the npe-a ethernet soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interf ace/signal is not required for any connection. utp_ip_data[7] / smii_rxdata[4] zvi vi vii utopia mode of operation: utopia input data. also known as rx_data. used by to the processor to receive data from an atm utopia level 2-compliant phy. mii mode of operation: not used. smii mode of operation: input data for smii interface number four. the data on this signal is received synchronously with respect to the rising edge of smii_clk when operat ing as an smii interface and synchronously with respect to the rising edge of smii_rxclk when operating as a source synchronous smii interface. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the utopia and/or the npe-a ethernet soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interf ace/signal is not required for any connection. table 15. utopia level 2/mii_a/ sm ii[4] interface (sheet 8 of 9) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? for information on selecting the desired interface, see the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 67 document number: 306261-003 utp_ip_addr[4:0] z z z vo o receive phy address bus. used by the processor when operating in mphy mode to poll and select a single phy at any one given time. utp_ip_fco z z z vo tri utopia input data flow control output signal: also known as the rx_enb_n. in sphy configurations, utp_ip_fco is used to inform the phy that the processor is ready to accept data. in mphy configurations, utp_ip_fco is used to select which phy will drive the utp_rx_data and utp_rx_soc signals. the phy is selected by placing the phy?s address on the utp_ip_addr and bringing utp_op_fco to logic 1 during the current clock, followed by the utp_op_fco going to a logic 0 on the next clock cycle. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. table 15. utopia level 2/mii_a/ sm ii[4] interface (sheet 9 of 9) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? for information on selecting the desired interface, see the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 68 document number: 306261-003 table 16. mii/smii interfaces (sheet 1 of 8) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description ethb_txclk / smii_clk zvi vi vii mii mode of operation: externally supplied transmit clock. ? 25 mhz for 100 mbps operation ? 2.5 mhz for 10 mbps this mac interface does not contain hardware hashing capabilities local to the interface. smii mode of operation: 125-mhz input clock used as the reference clo ck when operating in smii or source synchronous smii mode of operation. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. ethb_txdata[3:0] / smii_txdata[0] / smii_txdata[1] / smii_txdata[2] / smii_txdata[3] z 0 vo vo o mii mode of operation: transmit data bus to phy, asserted synchronously with respect to ethb_txclk. this mac interface does not contain hardware hashing capabilities local to the interface. smii mode of operation: each smii_txdata line is an interface to a separate physical port. ethb_txdata[3] is multiplexed with smii_txdata[3], ethb_txdata[2] is multiplexed with smii_txdata[2], ethb_txdata[1] is multiplexed with smii_txdata[1], ethb_txdata[0] is multiplexed with smii_txdata[0] the data on these signal are transmitted synchr onously with respect to the rising edge of smii_clk when operating as an smii interface and sy nchronously with respec t to the rising edge of smii_txclk when operating as a so urce synchronous smii interface note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? please refer to intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual for information on how to select the interface desired
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 69 document number: 306261-003 ethb_txen / smii_txclk z 0 vo vo o mii mode of operation: indicates that the phy is being presented with nibbles on the mii interface. asserted synchronously, with respect to ethb_txclk, at the first nibble of the preamble and remains asserted until all the nibbles of a frame are presented. this mac interface does not contain hardware hashing capabilities local to the interface. smii mode of operation: 125-mhz clock that is used to send data to a physical interface when operating in a source synchronous smii mode of operation. ethb_rxclk / smii_rxclk zvivovoi mii mode of operation: externally suppli ed receive clock. ? 25 mhz for 100 mbps operation ? 2.5 mhz for 10 mbps this mac interface does not contain hardware hashing capabilities local to the interface. smii mode of operation: 125-mhz clock that is used to sample data being received from a physical interface when operating in a source synchronous smii mode of operation. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. table 16. mii/smii interfaces (sheet 2 of 8) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? please refer to intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual for information on how to select the interface desired
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 70 document number: 306261-003 ethb_rxdata[3:0] / smii_rxdata[0] / smii_rxdata[1] / smii_rxdata[2] / smii_rxdata[3] zvi vi vii mii mode of operation: receive data bus from phy, data sampled synchr onously with respect to ethb_rxclk. this mac interface does not contain hardware hashi ng capabilities local to the interface. smii mode of operation: each smii_rxdata line is a separate physical port ethb_rxdata[3] is multiplexed with smii_rxdata[3], ethb_rxdata[2] is multiplexed with smii_rxdata[2], ethb_rxdata[1] is multiplexed with smii_rxdata[1], ethb_rxdata[0] is multiplexed with smii_rxdata[0] the data on these signal are received synchronousl y with respect to the rising edge of smii_clk when operating as an smii interface and synchro nously with respect to the rising edge of smii_rxclk when operating as a s ource synchronous smii interface when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the npe-b ethernet 0 and/or the npe ethernet 1-3 soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this in terface/signal is not required for any connection. one special configuration exists for the board designer. when npe b is configured in smii mode of operation and a subset of the four smii ports are utilized (i.e. all four are enabled but only two are being connected). the unused input s must be tied high with a 10-k ? resistor. table 16. mii/smii interfaces (sheet 3 of 8) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? please refer to intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual for information on how to select the interface desired
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 71 document number: 306261-003 ethb_rxdv / smii_rxsync zvi vi vii mii mode of operation: receive data valid, used to inform the mii interface that the ethernet phy is sending data. this mac interface does not contain hardware hash ing capabilities local to the interface. smii mode of operation: in source synchronous mode of operation, this signal is an input from a synchronous pulse created once every 10 smii_rxclk reference clocks to signal the start of the next 10 bits of data to be received. smii_rxclk reference clock operates at 125mhz. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the npe-b ethernet 0 and/or the npe ethernet 1-3 soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this in terface/signal is not required for any connection. ethb_col z vi vi vi i mii mode of operation: asserted by the phy when a collision is detect ed by the phy. this mac interface does not contain hardware hashing capabilities local to the interface. ? when npe b is configured in mii mode of operation and the signal is not being used, it should be pulled low through a 10-k ? resistor. smii mode of operation: not used. ? when npe b is configured in smii mode of operat ion, this signal must be pulled high with a 10-k ? resistor. when this interface is disabled via the npe-b ethernet 0 and/or the npe ethernet 1-3 soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interface/signal is not required for any connection. table 16. mii/smii interfaces (sheet 4 of 8) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? please refer to intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual for information on how to select the interface desired
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 72 document number: 306261-003 ethb_crs/ smii_sync/ smii_txsync z z z vi / vo i/o mii mode of operation: asserted by the phy when the transmit medium or receive medium is active. de-asserted when both the transmit and receive medium are idle. remains asserted throughout the duration of a collision condition. phy asserts crs asynch ronously and de-asserts synchronously, with respect to ethb_rxclk. this mac interface does not contain hardwar e hashing capabilities local to the interface. smii mode of operation: in smii mode of operation, this signal is an output that creates a synchronous pulse once every 10 smii_clk reference clocks to signal the start of the next 10 bits of data to be transmitted/ received. smii_clk reference clock operates at 125mhz. in source synchronous mode of operation, a synchronous pulse output created once every 10 smii_txclk clocks to signal the start of the nex t 10 bits of data to be transmitted. smii_txclk operates at 125mhz. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. when this interface is disabled via the npe-b ethernet 0 and/or the npe ethernet 1-3 soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this in terface/signal is not required for any connection. in mii mode of operation, this signal is a valid input. in smii mode of operation this signal is a valid output. eth_mdio z z z vb i/o management data output. provides the write data to both phy devices connected to each mii interface. an external pull-up resistor of 1. 5k ohm is required on eth_mdio to properly quantify the external phys used in the system. for specific implementation, see the ieee 802.3 specification. should be pulled high through a 10-k ? resistor when not being utilized in the system. eth_mdc z z vi vi / vo i/o management data clock. management data interface cl ock is used to clock the mdio signal as an output and sample the mdio as an input. the eth_mdc is an input on power up and can be configured to be an output through an intel api as documented in the intel ? ixp400 software programmer?s guide . table 16. mii/smii interfaces (sheet 5 of 8) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? please refer to intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual for information on how to select the interface desired
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 73 document number: 306261-003 ethc_txclk z vi vi vi i externally supplied transmit clock. ? 25 mhz for 100 mbps operation ? 2.5 mhz for 10 mbps this mac contains hardware hashing ca pabilities local to the interface. this signal should be pulled high through a 10-k ? resistor when being utilized in smii mode of operation. when this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-k ? resistor. ethc_txdata[3:1] z 0 vo vo o mii mode of operation: transmit data bus to phy, asserted synchronously with respect to ethc_txclk. this mac contains hardware hashing capabilities local to the interface. smii mode of operation: not used in smii mode of operation. ethc_txdata[0] / smii_txdata[5] z 0 vo vo o mii mode of operation: transmit data bus to phy, asserted synchronously with respect to ethc_txclk. this mac contains hardware hashing capabilities local to the interface. smii mode of operation: the data on this signal is transmitted synchronous ly with respect to the rising edge of smii_clk when operating as an smii interface and synchro nously with respect to the rising edge of smii_txclk when operating as a source synchronous smii interface ethc_txen z 0 vo vo o indicates that the phy is being presented with nibbles on the mii interface. asserted synchronously, with respect to ethc_txclk, at the first nibble of the preamble, and remains asserted until all the nibbles of a frame ar e presented. this mac c ontains hardware hashing capabilities local to the interface. table 16. mii/smii interfaces (sheet 6 of 8) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? please refer to intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual for information on how to select the interface desired
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 74 document number: 306261-003 ethc_rxclk z vi vi vi i externally suppli ed receive clock. ? 25 mhz for 100 mbps operation ? 2.5 mhz for 10 mbps this mac contains hardware hashing ca pabilities local to the interface. should be pulled high through a 10-k ? resistor when not being utilized in the system or when in smii mode of operation. ethc_rxdata[3:1] z vi vi vi i receive data bus from phy, data sampled synchr onously, with respect to ethc_rxclk. this mac contains hardware hashing capabi lities local to the interface. ? not used when operating in smii mode of operation. should be pulled high through a 10-k ? resistor when not being utilized in the system or when in smii mode of operation. ethc_rxdata[0] / smii_rxdata[5] zvi vi vii mii mode of operation: receive data bus from phy, data sampled synchr onously, with respect to ethc_rxclk. this mac contains hardware hashing capabi lities local to the interface smii mode of operation: the data on this signal is received synchronously with respect to the rising edge of smii_clk when operating as an smii interface and synchro nously with respect to the rising edge of smii_rxclk when operating as a s ource synchronous smii interface should be pulled high through a 10-k ? resistor when not being utilized in the system. ethc_rxdv z vi vi vi i receive data valid, used to inform the mii interface that the ethernet phy is sending data. this mac contains hardware hashing ca pabilities local to the interface. should be pulled high through a 10-k ? resistor when not being utilized in the system. table 16. mii/smii interfaces (sheet 7 of 8) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? please refer to intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual for information on how to select the interface desired
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 75 document number: 306261-003 ethc_col z vi vi vi i mii mode of operation: asserted by the phy when a collision is detect ed by the phy. this mac contains hardware hashing capabilities local to the interface. ? when npe c is configured in mii mode of operation and the signal is not being used, it should be pulled low through a 10-k ? resistor. smii mode of operation: not used. ? when npe c is configured in smii mode of operation, this signal must be pulled high through a 10-k ? resistor. when this interface is disabled via the npe-c et hernet soft fuse (refer to the expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual ) and is not being used a system desing, this interface/signal is not required for any connection. ethc_crs z vi vi vi i asserted by the phy when the transmit medium or receive medium are active. de-asserted when both the transmit and receive medium are idle. remains asserted throughout the duration of collision condition. phy asserts crs a synchronously and de-asserts synchronously with respect to ethc_rxclk. this mac contains hardware hashing ca pabilities local to the interface. should be pulled high through a 10-k ? resistor when not being utilized in the system or when in smii mode of operation. table 16. mii/smii interfaces (sheet 8 of 8) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? please refer to intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual for information on how to select the interface desired
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 76 document number: 306261-003 table 17. expansion bus interface (sheet 1 of 4) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description ex_clk z vi vi vi i input clock signal used to sample all expansion interface inputs and clock all expansion interface outputs. ex_ale h h vo vo / z tri expansion bus address-latch enable used for multiplexed address/data bus accesses, as an advance pin for intel synchronous modes of operat ion/zbt sram mode of operation, and ld_n for zbt sram. ex_ale is always used by outbound transfers. ex_addr[24:0] h h vb vb i/o expansion bus address used as an output for data accesses over the expansion bus when executing outbound transactions and used as an input for data accesses over the expansion bus when executing inbound transactions. also, used as an input during reset to capture device configuration. these signals have a weak pull-up resistor attached internally. based on the desired configuration, various address signals must be tied low in order for the device to operate in the desired mode. a 4.7 k ? pull-down resistor is required to over ride these pull-up resistors. these pull- ups are disabled when pll_lock is asserted and the ixp45x/ixp46x network processors drive the signal based upon grant. ex_addr is driven by ixp45x/ixp46x network processors except when grant is asserted to an external master or during reset. very important note: see intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual for additional details on address strapping. ex_wr_n h h vb vb i/o expansion bus write enable signal is used as an intel-mode write strobe / motorola-mode data strobe (exp_mot_ds_n) / ti*-mode data strobe (ti_hds1_n) / zbt sram mode read/ write_n(zbt_rd_wr_n) for outbound transactions . this signal is an output for outbound transactions. expansion bus write enable signal is used as a wr ite enable signal to the ixp45x/ixp46x network processors for inbound transacti on support. this signal is an input for inbound transactions. ex_wr_n is driven by ixp45x/ixp46x network proc essors unless grant is asserted to an external master ex_rd_n h h vb vb i/o expansion bus read enable signal is used as an intel-mode read strobe / motorola-mode read-not- write (expb_mot_rnw) / ti mode read-not-write (ti_hr_w_n) / zbt sram mode output enable (zbt_oe_n) for outbound transactions. this si gnal is an output for outbound transactions. expansion bus read enable signal is used as a read enable signal to the ixp45x/ixp46x network processors for inbound transacti on support. this signal is an input for inbound transactions. ex_rd_n is driven by ixp45x/ixp46x network proc essors unless grant is asserted to an external master. note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 77 document number: 306261-003 ex_cs_n[7:0] h h vb vb i/o used to drive chip selects for outbound transactions for the expansion bus. ? chip selects 0 through 7 can be configured to support intel/intel synchronous/motorola/zbt sram bus cycles. ? chip selects 4 through 7 can be confi gured to support ti hpi bus cycles. ? these signal are also sampled by the arbiter to determine when to arbitrate. driving the signals from an external interface has no effect on the operation of anything but the arbiter. ? external board pull-ups are required on ex_cs_n to ensure this signal remains deasserted (especially in a multi-master environment). a dditionally, the system desi gner is responsible for ensuring that all the tri-stated signals do not become indeterminate. if they become indeterminate, excessive power consumption will occur in the pad input buffers. ex_data[31:0] h h vb vb i/o expansion bus, bidirectional data ex_be_n[3:0] h h vb vb i/o expansion bus byte enables. ex_be_n is used to select the particular bytes that will be written or read when executing outbound transfers. when executing inbound transfers, ex_be_n will be us ed to select sub-word writes. only 32 bit reads of the expansion bus is supported when operating on inbound transfers. ex_be_n is driven by the ixp45x/ixp46x network processors unless grant is asserted to an external master. ex_iowait_n z vi vi vi i data ready/acknowledge from expansion bus devic es. expansion bus access is halted when an external device sets ex_iowait_n to logic 0 and resume from the halted location once the external device sets ex_iowait_n to logic 1. this signal affects accesses that use ex_cs_n[7:0] when the chip select is configured in intel and motorola modes of operation. during idle cycles, the board is responsible for ensuring that ex_iowait_n is pulled-up. additionally, ex_iowait_n must always be pul led high during micron zbt, intel synchronous mode, and hpi cycles should be pulled high through a 10-k ? resistor when not being utilized in the system. ex_rdy_n[3:0] z vi vi vi i hpi interface ready signals. can be configured to be active high or active low. these signals are used to halt accesses using chip selects 7 through 4 when the chip selects are configured to operate in hpi mode. there is one rdy signal per chip select. this signal only affects accesses that use ex_cs_n[7:4]. should be pulled high through a 10-k ? resistor when not being utilized in the system. table 17. expansion bus interface (sheet 2 of 4) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 78 document number: 306261-003 ex_parity[3:0] h h vb vb i/o byte wide parity protection on the ex_data[31:0] ex_req_n[3:1] z h vi/h* vi/h* i signals used by external masters to gain access to the bus. an external master asserts this signal to the internal arbiter to request access to use the expans ion bus signals. * when configured in external arbiter mode of operat ion, an internal pull-up will be enabled, thus the pins will be driven to vcc should be pulled high through a 10-k ? resistor when not being utilized in the system. ex_req_gnt_n z vi vi vi i when the ixp45x/ixp46x network processors are fu nctioning as the expansion bus arbiter, this signal will serve as the request i nput from an external master. if there is an external arbiter used for expansion bus accesses, this signal will serve as the expansion bu s grant input from the external arbiter. should be pulled high through a 10-k ? resistor when not being utilized in the system. ex_gnt_n[3:1] z b?111 vo vo o signals used by the arbiter to inform external mast ers that the master is now granted access to use the bus. in response to an ex_req_n being asserted by an external master, the arbiter will output the corresponding ex_gnt_n signal to inform the exte rnal master that the expansion bus is clear for that master to utilize. ex_gnt_req_n z 1 vo vo o when the ixp45x/ixp46x network processors are fu nctioning as the expansion bus arbiter, this signal will serve as the grant output for an exte rnal master asserting the corresponding request. if there is an external arbiter used for expansion bus accesses, this signal will serve as the expansion bus request output signal to the external arbiter. ex_slave_cs_n z vi vi vi i the expansion bus chip select input is used to de termine when an external master is attempting to access the ixp45x/ixp46x network processors? ex pansion bus interface and internal memory map of the processors. should be pulled high through a 10-k ? resistor when not being utilized in the system. table 17. expansion bus interface (sheet 3 of 4) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 79 document number: 306261-003 ex_burst z vi vi vi i for inbound transfers, this signal is used to signify that a burst operation is being requested to occur. should be pulled high through a 10-k ? resistor when not being utilized in the system. ex_wait_n h h h vo/h tri expansion bus ixp45x/ixp46x network processors wait. ex_wait_n is driven by the processors when ex_slave_cs_n is asserted. after the de-assertion of ex_slave_cs_n, the ixp45x/ ixp46x network processors will st op driving this signal. a pull-up in the pad io is enabled all the time to prevent this bus from fl oating or transitioning to vss. this signal is used to hold off an external master when the expansion interface c annot be accessed immediately. most commonly seen when a read access of the interface is occurring and the data has not been returned from the internal peripheral unit to the expansion interface. table 18. uart interfaces (sheet 1 of 2) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description rxdata0 z vi vi vi i uart serial data input to uart pins. should be pulled high through a 10-k ? resistor when not being utilized in the system. txdata0 z v0 vo vo o uart serial data output. the txd signal is set to the marking (logic 1) state upon a reset operation. note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . table 17. expansion bus interface (sheet 4 of 4) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 80 document number: 306261-003 cts0_n h vi/h vi/h vi/h i uart clear-to-send input to uart pins. when logic 0, this pin indicates that the modem or data set connected to the uart interface of the processor is ready to exchange data. the signal is a modem status input whose condition can be tested by the processor. should be pulled high through a 10-k ? resistor when not being utilized in the system. rts0_n z v0 vo vo o uart request-to-send output: when logic 0, this informs the modem or the dat a set connected to the uart interface of the processor that the uart is ready to exchange data. a reset sets the request to send signal to logic 1. loop-mode operation holds this signal in its inactive state (logic 1) rxdata1 z vi vi vi i uart serial data input. should be pulled high through a 10-k ? resistor when not being utilized in the system. txdata1 z vo vo vo o uart serial data output. the txd signal is set to the marking (logic 1) state upon a reset operation. cts1_n h vi/h vi/h vi/h i uart clear-to-send input to uart pins. when logic 0, this pin indicates that the modem or data set connected to the uart interface of the processor is ready to exchange data. the signal is a modem status input whose condition can be tested by the processor. should be pulled high through a 10-k ? resistor when not being utilized in the system. rts1_n z v0 vo vo o uart request-to-send output: when logic 0, this informs the modem or the dat a set connected to the uart interface of the processor that the uart is ready to exchange data. a reset sets the request to send signal to logic 1. loop-mode operation holds this signal in its inactive state (logic 1). table 18. uart interfaces (sheet 2 of 2) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 81 document number: 306261-003 table 19. serial periph eral port interface name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description ssp_sclk z 0 vo vo o ssp_sclk is the serial bit clock used to control the timing of a transfer. ssp_sclk can be generated internally (master mode) as defined by a c ontrol register bit internal to the ixp45x/ixp46x network processors. ssp_sfrm z 1 vo vo o ssp_sfrm is the serial frame indicator that indi cates the beginning and the end of a serialized data word. the ssp_sfrm can be generated internally (mas ter mode) or taken from an external source (slave mode) as defined by a control register bit internal to the ixp45x/ixp46x network processors. this signal may be active low or active high depending upon the mode of operation. please refer to the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual for additional details. ssp_txd z 0 vo vo o ssp_txd is the transmit data (serial data out) serializ ed data line. sample length is a function of the selected serial data sample size. ssp_rxd z vi vi vi i ssp_rxd is the receive data (serial data in) serialized data line. sample length is a function of the selected serial data sample size. should be pulled high through a 10-k ? resistor when not being utilized in the system. ssp_extclk z vi vi vi i ssp_extclk is an external clock which can be select ed to replace the internal 3.6864 mhz clock. the ssp_extclk input is selected by setting vari ous internal registers to appropriate values. should be pulled high through a 10-k ? resistor when not being utilized in the system. note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 82 document number: 306261-003 table 20. i 2 c interface name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description i2c_sda z z vod vod i/o/od the receive and transmit data/address line used to communicate between various master and slave i 2 c interfaces. a pull up resistor is required on this interface. please refer to the i 2 c specification. i2c_scl z z vod vod i/o/od the master and slave clock line used to co mmunicate between various master and slave i 2 c interfaces. a pull up resistor is required on this interface. please refer to the i 2 c specification. note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 83 document number: 306261-003 table 21. usb host/device interfaces (sheet 1 of 2) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description usb_dpos z z vb vb i/o positive signal of the differential usb receiver/driver for the usb device interface. note: this pin requires an 18 ? external series resistor. this resistor is located after the pin, but before the pull-down resistor. when this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled low with a 10-k ? resistor. when this interface is di sabled via the usb device soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interface/signal is not required for any connection. usb_dneg z z vb vb i/o negative signal of the differential usb rece iver/driver for the usb device interface. note: this pin requires an 18 ? external series resistor. this resistor is located after the pin, but before the pull-down resistor. when this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled low with a 10-k ? resistor. when this interface is di sabled via the usb device soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interface/signal is not required for any connection. usb_hpos z z vb vb i/o positive signal of the differential usb receiver/driver for the usb host interface. note: this pin requires an 20 ? external series resistor. this resistor is located after the pin, but before the pull-down resistor. when this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled low with a 10-k ? resistor. when this interface is di sabled via the usb device soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interface/signal is not required for any connection. note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? please refer to the intel? ixp45x and intel? ixp46x product line of network processors hardware design guidelines for additional board design details.
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 84 document number: 306261-003 usb_hneg z z vb vb i/o negative signal of the differential usb receiver/driver for the usb host interface. note: this pin requires an 20 ? external series resistor. this resistor is located after the pin, but before the pull-down resistor. when this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled low with a 10-k ? resistor. when this interface is di sabled via the usb device soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interface/signal is not required for any connection. usb_hpen z z vo vo o enable to the external vbus power source usb_hpwr z z vi vi i external vbus power is in over current condition when this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled high with a 10-k ? resistor. when this interface is di sabled via the usb device soft fuse (refer to expansion bus controller chapter of the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual) and is not being used in a system design, this interface/signal is not required for any connection. table 22. oscillator interface name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description osc_in n/a vi vi vi i 33.33-mhz, sinusoidal input signal. can be driven by an oscillator. osc_out n/a vo vo vo o 33.33-mhz, sinusoidal output signal . left disconnected when being driven by an oscillator. note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . table 21. usb host/device interfaces (sheet 2 of 2) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . ?? please refer to the intel? ixp45x and intel? ixp46x product line of network processors hardware design guidelines for additional board design details.
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 85 document number: 306261-003 table 23. gpio interface name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description gpio[12:0] z z vi vb i/o general purpose input/output pins. may be configured as an input or an output. as an input, each signal may be configured a processor interrupt. default after re set is to be configured as inputs. some gpio may serve as an optional alternate function. refer to section 3.1.12, ?gpio? on page 28 , for additional details on alternate function mapping. should be pulled high using a 10-k ? resistor when not being utilized in the system. gpio[13] z z vi vb i/o general purpose input/output pins. may be configured as an input or an output. default after reset is to be configured as inputs. some gpio may serve as an optional alternate function. refer to section 3.1.12, ?gpio? on page 28 , for additional details on alternate function mapping. should be pulled high using a 10-k ? resistor when not being utilized in the system. gpio[14] z z vi vb i/o can be configured the same as gpio pin 13 or as a clock output. configuration as an output clock can be set at various speeds of up to 33 mhz with various duty cycles. configured as an input, upon reset. some gpio may serve as an opt ional alternate function. refer to section 3.1.12, ?gpio? on page 28 , for additional details on alternate function mapping. should be pulled high through a 10-k ? resistor when not being utilized in the system. gpio[15] z clkout / vo vo vb i/o can be configured the same as gpio pin 13 or as a clock output. configuration as an output clock can be set at various speeds of up to 33 mhz with various duty cycles. configured as an output, upon reset. can be used to clock the expansion interface, after rese t. some gpio may serve as an optional alternate function. refer to section 3.1.12, ?gpio? on page 28 , for additional details on alternate function mapping. should be pulled high through a 10-k ? resistor when not being utilized in the system. the interface should be set to an input in the not used configuration. note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 86 document number: 306261-003 table 24. jtag interface name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description jtg_tms h vi / h vi/h vi/h i test mode select for the ieee 1149.1 jtag interface. jtg_tdi h vi /h vi/h vi/h i input data for the ieee 1149.1 jtag interface. jtg_tdo z vo/z vo / z vo / z tri output data for the ieee 1149.1 jtag interface. jtg_trst_n h vi/h vi vi i used to reset the ieee 1149.1 jtag interface. important: the jtg_trst_n signal must be asserted (driven low) during power-up, otherwise the tap controller will not be initialized properly and the processor may be locked. when the jtag interface is not being used , the signal must be pulled low using a 10-k ? resistor. jtg_tck z vi vi vi i used as the clock for the ieee 1149.1 jtag interface. note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 . table 25. system interface (sheet 1 of 2) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description bypass_clk z vi vi vi i used for test purposes only. must be pulled high using a 10-k ? resistor for normal operation. scantestmode_n vi/h vi/h vi / h vi / h i used for test purposes only. must be pulled high using a 10-k ? resistor for normal operation. note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 87 document number: 306261-003 reset_in_n vi/h vi/h vi / h vi / h i used as a reset input to the device after power up conditions have been met. power up conditions include the power s upplies reaching a safe stable co ndition and the pll achieving a locked state and the pwron_reset_n coming to an active state prior to the reset_in_n coming to an active state. pwron_reset_n vi/h vi/h v i/ h vi / h i signal used at power up to reset all internal logi c to a known state after the pll has achieved a locked state. the pwron_reset_n signal is a 3.3-v signal. highz_n vi / h vi / h vi / h vi / h i used for test purposes only. must be pulled high using a 10-k ? resistor for normal operation. pll_lock z vo vo vo o signal used to inform external reset logic that the internal pll has achieved a locked state. pll_lock will also be de-asserted during a watchdog timeout. rcomp_ref tied off to a resistor tied off to a resistor tied off to a resistor tied off to a resistor o signal used to control pci and smii drive strength characteristics. drive strength is varied on pci and smii signals depending upon temperature. pin requires a 34- ? +/- 1% tolerance resistor to ground. (refer to figure 14 on page 119 .) spare1 n/a n/a n/a n/a n/a no connection is to be made to this signal spare2 n/a n/a n/a n/a n/a no connection is to be made to this signal table 25. system interface (sheet 2 of 2) name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description note: this table discusses all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processors. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 88 document number: 306261-003 table 26. power interface name power on reset ? reset ? normal after reset until software enables normal after software enables type ? description v cc n/a n/a n/a n/a i 1.3-v power supply input pins used for the internal logic. if operating at 667 mhz, this supply voltage needs to be increased to vcc = 1.5 v. v ccp n/a n/a n/a n/a i 3.3-v power supply input pi ns used for the peripheral (i/o) logic. v ccm n/a n/a n/a n/a i 2.5-v power supply input pins used for the ddr memory interface v ss n/a n/a n/a n/a i ground power supply input pins used for bot h the 3.3-v, 2.5-v, and the 1.3-v power supplies. osc_vccp n/a n/a n/a n/a i 3.3-v power supply input pins used for the peripheral (i/o) logic of the analog oscillator circuitry. require special power filtering circuitry. refer to figure 12 on page 118 . osc_vssp n/a n/a n/a n/a i ground input pins used for the peripheral (i/o) l ogic of the analog oscillator circuitry. used in conjunction with the osc_vccp pins. requires special power filtering circuitry. refer to figure 12 on page 118 . osc_vcc n/a n/a n/a n/a i 1.3-v power supply input pins used for the internal logic of the analog oscillat or circuitry. requires special power filtering circuitry. if operating at 667 mhz, this supply voltage needs to be increased to vcc = 1.5 v. refer to figure 13 on page 119 . osc_vss n/a n/a n/a n/a i ground power supply input pins used for the internal logic of the analog oscillat or circuitry. used in conjunction with the osc_vcc pins. requires special power filtering circuitry. refer to figure 13 on page 119 . v ccpll1 n/a n/a n/a n/a i 1.3-v power supply input pins used for the inte rnal logic of the analog phase lock-loop circuitry. requires special power filtering circuitry. if o perating at 667 mhz, this supply voltage needs to be increased to vcc = 1.5 v. refer to figure 9 on page 117 . v ccpll2 n/a n/a n/a n/a i 1.3-v power supply input pins used for the inte rnal logic of the analog phase lock-loop circuitry. requires special power filtering circuitry. if o perating at 667 mhz, this supply voltage needs to be increased to vcc = 1.5 v. refer to figure 10 on page 117 . v ccpll3 n/a n/a n/a n/a i 1.3-v power supply input pins used for the inte rnal logic of the analog phase lock-loop circuitry. requires special power filtering circuitry. if o perating at 667 mhz, this supply voltage needs to be increased to vcc = 1.5 v. refer to figure 11 on page 118 . note: this table discusse s all features supported on the intel ? ixp45x and intel ? ixp46x product line of network processo rs. for details on feature support listed by processor, see table 1 on page 14 . ? for a legend of the type codes, see table 10 on page 46 .
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 89 4.3 signal-pin descriptions when designing with a multifunction processor, sometimes a board design may be built to allow a group of products to be produced from a single board design. when this occurs, some features of a given processor may not be used. the intel? ixp45x and intel? ixp46x product line of network processors hardware design guidelines gives the system designer a guide to determine how the signals must be conditioned and how the part behaves under given configurations. table 27. processors? ball map assignments (sheet 1 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 a1 vss x x x a2 vss x x x a3 ddri_cb[0] x x a4 ddri_ck_n[1] x x x a5 ddri_dm[3] x x x a6 ddri_dq[30] x x x a7 ddri_dq[26] x x x a8 ddri_dq[25] x x x a9 ddri_dq[22] x x x a10 ddri_dq[18] x x x a11 ddri_ma[4] x x x a12 vss x x x a13 ddri_ma[0] x x x a14 ddri_ma[8] x x x a15 ddri_ba[1] x x x a16 vccm x x x a17 ddri_cs_n[1] x x x a18 ddri_cas_n x x x a19 ddri_dm[1] x x x a20 ddri_dq[13] x x x a21 ddri_dq[11] x x x a22 ddri_dm[0] x x x a23 ddri_dq[6] x x x a24 vccm x x x a25 vss x x x a26 vss x x x note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no physical ball on package.
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 90 document number: 306261-003 b1 vss x x x b2 vss x x x b3 ddri_cb[2] x x b4 ddri_cb[1] x x b5 ddri_ck[1] x x x b6 ddri_dqs[3] x x x b7 ddri_dq[31] x x x b8 ddri_dq[24] x x x b9 ddri_dq[21] x x x b10 ddri_dq[23] x x x b11 ddri_dq[17] x x x b12 ddri_ma[5] x x x b13 ddri_ma[7] x x x b14 ddri_ma[9] x x x b15 ddri_ma[11] x x x b16 ddri_cs_n[0] x x x b17 ddri_ras_n x x x b18 ddri_vref x x x b19 ddri_dqs[1] x x x b20 ddri_dq[14] x x x b21 ddri_dqs[0] x x x b22 ddri_dq[5] x x x b23 ddri_dq[7] x x x b24 vccp x x x b25 usb_hpen x x x b26 vss x x x table 27. processors? ball map assignments (sheet 2 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no phys ical ball on package.
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 91 c1 pci_ad[30] x x x c2 pci_gnt_n[0] x x x c3 ddri_cb[3] x x c4 ddri_cb[5] x x c5 ddri_cb[7] x x c6 ddri_dqs[4] x x x c7 ddri_dq[28] x x x c8 ddri_dq[27] x x x c9 ddri_dm[2] x x x c10 vccm x x x c11 ddri_dq[16] x x x c12 vss x x x c13 ddri_ma[1] x x x c14 vccm x x x c15 ddri_ba[0] x x x c16 ddri_cke[0] x x x c17 ddri_ck[0] x x x c18 ddri_rcvenout_n x x x c19 ddri_dq[15] x x x c20 ddri_dq[10] x x x c21 ddri_dq[4] x x x c22 ddri_dq[3] x x x c23 ddri_dq[2] x x x c24 vss x x x c25 ex_cs_n[2] x x x c26 ex_cs_n[5] x x x table 27. processors? ball map assignments (sheet 3 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no physical ball on package.
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 92 document number: 306261-003 d1 vccp x x x d2 pci_req_n[1] x x x d3 pci_gnt_n[1] x x x d4 vss x x x d5 ddri_cb[4] x x d6 ddri_cb[6] x x d7 ddri_dm[4] x x x d8 ddri_dq[29] x x x d9 vss x x x d10 ddri_dqs[2] x x x d11 ddri_dq[19] x x x d12 ddri_ma[3] x x x d13 ddri_ma[6] x x x d14 ddri_ma[10] x x x d15 ddri_ma[13] x x x d16 ddri_cke[1] x x x d17 ddri_ck_n[0] x x x d18 ddri_dq[12] x x x d19 ddri_dq[9] x x x d20 ddri_dq[8] x x x d21 vccm x x x d22 ddri_dq[1] x x x d23 ddri_dq[0] x x x d24 ex_cs_n[1] x x x d25 ex_cs_n[4] x x x d26 vccp x x x table 27. processors? ball map assignments (sheet 4 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no phys ical ball on package.
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 93 e1 pci_ad[26] x x x e2 pci_ad[28] x x x e3 pci_req_n[0] x x x e4 pci_gnt_n[2] x x x e5 vss x x x e6 vss x x x e7 vccm x x x e8 vccm x x x e9 vccm x x x e10 vss x x x e11 ddri_dq[20] x x x e12 vccm x x x e13 ddri_ma[2] x x x e14 vss x x x e15 ddri_ma[12] x x x e16 ddri_we_n x x x e17 ddri_rcvenin_n x x x e18 vss x x x e19 vss x x x e20 vccm x x x e21 vss x x x e22 vss x x x e23 usb_hpwr x x x e24 ex_cs_n[3] x x x e25 ex_gnt_n[1] x x x e26 ex_req_n[2] x x x table 27. processors? ball map assignments (sheet 5 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no physical ball on package.
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 94 document number: 306261-003 f1 pci_ad[21] x x x f2 pci_cbe_n[3] x x x f3 vccp x x x f4 pci_ad[31] x x x f5 pci_gnt_n[3] x x x f6 vss x x x f7 ddri_ck[2] x x x f8 vss x x x f9 vccm x x x f10 vcc x x x f11 vcc x x x f12 vcc x x x f13 vcc x x x f14 vcc x x x f15 vcc x x x f16 vcc x x x f17 vss x x x f18 vss x x x f19 vss x x x f20 vss x x x f21 spare1 x x x f22 vss x x x f23 ex_cs_n[0] x x x f24 ex_gnt_req_n x x x f25 ex_req_n[1] x x x f26 vss x x x table 27. processors? ball map assignments (sheet 6 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no phys ical ball on package.
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 95 g1 pci_ad[18] x x x g2 pci_ad[20] x x x g3 pci_ad[22] x x x g4 pci_ad[25] x x x g5 pci_req_n[3] x x x g6 pci_inta_n x x x g7 rcomp_ref x x x g8 ddri_ck_n[2] x x x g9 vcc x x x g10 vcc x x x g11 g12 g13 g14 g15 g16 g17 vcc x x x g18 vcc x x x g19 vcc x x x g20 ddri_rcomp x x x g21 usb_dpos x x x g22 usb_hpos x x x g23 ex_slave_cs_n x x x g24 ex_req_gnt_n x x x g25 ex_addr[22] x x x g26 ex_addr[18] x x x table 27. processors? ball map assignments (sheet 7 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no physical ball on package.
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 96 document number: 306261-003 h1 vccp x x x h2 pci_ad[17] x x x h3 vss x x x h4 pci_ad[24] x x x h5 pci_ad[29] x x x h6 pci_req_n[2] x x x h7 pci_serr_n x x x h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 h20 usb_dneg x x x h21 usb_hneg x x x h22 ex_cs_n[7] x x x h23 ex_gnt_n[3] x x x h24 ex_addr[23] x x x h25 ex_addr[21] x x x h26 ex_addr[17] x x x table 27. processors? ball map assignments (sheet 8 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no phys ical ball on package.
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 97 j1 pci_clkin x x x j2 pci_frame_n x x x j3 pci_ad[16] x x x j4 pci_ad[19] x x x j5 pci_ad[23] x x x j6 pci_ad[27] x x x j7 vcc x x x j8 j9 j10 j11 j12 j13 j14 j15 j16 j17 j18 j19 j20 vcc x x x j21 ex_cs_n[6] x x x j22 vss x x x j23 ex_addr[24] x x x j24 ex_addr[20] x x x j25 ex_addr[5] x x x j26 vccp x x x table 27. processors? ball map assignments (sheet 9 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no physical ball on package.
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 98 document number: 306261-003 k1 vss x x x k2 pci_devsel_n x x x k3 pci_cbe_n[2] x x x k4 pci_stop_n x x x k5 vss x x x k6 pci_idsel x x x k7 vcc x x x k8 k9 k10 k11 k12 k13 k14 k15 k16 k17 k18 k19 k20 vcc x x x k21 ex_gnt_n[2] x x x k22 ex_req_n[3] x x x k23 ex_addr[19] x x x k24 ex_addr[4] x x x k25 ex_rd_n x x x k26 ex_clk x x x table 27. processors? ball map assignments (sheet 10 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no phys ical ball on package.
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 99 l1 pci_ad[11] x x x l2 pci_cbe_n[1] x x x l3 pci_perr_n x x x l4 pci_par x x x l5 pci_irdy_n x x x l6 vcc x x x l7 l8 l9 l10 l11 vss x x x l12 vss x x x l13 vss x x x l14 vss x x x l15 vss x x x l16 vss x x x l17 l18 l19 l20 l21 vcc x x x l22 vccp x x x l23 ex_ale x x x l24 ex_be_n[0] x x x l25 ex_be_n[2] x x x l26 ex_be_n[3] x x x table 27. processors? ball map assignments (sheet 11 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no physical ball on package.
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 100 document number: 306261-003 m1 pci_cbe_n[0] x x x m2 pci_ad[12] x x x m3 pci_ad[14] x x x m4 pci_ad[13] x x x m5 pci_ad[15] x x x m6 vcc x x x m7 m8 m9 m10 m11 vss x x x m12 vss x x x m13 vss x x x m14 vss x x x m15 vss x x x m16 vss x x x m17 m18 m19 m20 m21 vcc x x x m22 ex_wr_n x x x m23 ex_be_n[1] x x x m24 vss x x x m25 ex_iowait_n x x x m26 ex_rdy_n[0] x x x table 27. processors? ball map assignments (sheet 12 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no phys ical ball on package.
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 101 n1 pci_ad[6] x x x n2 pci_ad[4] x x x n3 vccp x x x n4 pci_ad[10] x x x n5 pci_ad[9] x x x n6 vcc x x x n7 n8 n9 n10 n11 vss x x x n12 vss x x x n13 vss x x x n14 vss x x x n15 vss x x x n16 vss x x x n17 n18 n19 n20 n21 vcc x x x n22 ex_addr[3] x x x n23 ex_addr[2] x x x n24 ex_rdy_n[1] x x x n25 ex_rdy_n[2] x x x n26 ex_rdy_n[3] x x x table 27. processors? ball map assignments (sheet 13 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no physical ball on package.
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 102 document number: 306261-003 p1 vss x x x p2 pci_trdy_n x x x p3 pci_ad[2] x x x p4 pci_ad[8] x x x p5 pci_ad[0] x x x p6 vcc x x x p7 p8 p9 p10 p11 vss x x x p12 vss x x x p13 vss x x x p14 vss x x x p15 vss x x x p16 vss x x x p17 p18 p19 p20 p21 vcc x x x p22 ex_data[23] x x x p23 ex_parity[1] x x x p24 ex_parity[2] x x x p25 ex_burst x x x p26 ex_wait_n x x x table 27. processors? ball map assignments (sheet 14 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no phys ical ball on package.
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 103 r1 pci_ad[7] x x x r2 pci_ad[5] x x x r3 pci_ad[3] x x x r4 pci_ad[1] x x x r5 hss_txframe0 x x r6 vcc x x x r7 r8 r9 r10 r11 vss x x x r12 vss x x x r13 vss x x x r14 vss x x x r15 vss x x x r16 vss x x x r17 r18 r19 r20 r21 vcc x x x r22 vcc x x x r23 ex_data[21] x x x r24 ex_data[22] x x x r25 ex_data[15] x x x r26 vccp x x x table 27. processors? ball map assignments (sheet 15 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no physical ball on package.
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 104 document number: 306261-003 t1 hss_txdata0 x x t2 hss_txclk0 x x t3 hss_rxframe0 x x t4 hss_rxdata0 x x t5 hss_rxclk0 x x t6 ethc_txen x x x t7 t8 t9 t10 t11 vss x x x t12 vss x x x t13 vss x x x t14 vss x x x t15 vss x x x t16 vss x x x t17 t18 t19 t20 t21 vcc x x x t22 ex_data[17] x x x t23 ex_data[11] x x x t24 vss x x x t25 ex_data[13] x x x t26 ex_data[14] x x x table 27. processors? ball map assignments (sheet 16 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no phys ical ball on package.
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 105 u1 hss_txframe1 x x u2 hss_txdata1 x x u3 vccp x x x u4 hss_txclk1 x x u5 vss x x x u6 ethc_rxdv x x x u7 vcc x x x u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 vcc x x x u21 ex_data[28] x x x u22 ex_data[30] x x x u23 ex_data[16] x x x u24 ex_data[18] x x x u25 ex_data[12] x x x u26 ex_data[20] x x x table 27. processors? ball map assignments (sheet 17 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no physical ball on package.
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 106 document number: 306261-003 v1 hss_rxframe1 x x v2 hss_rxdata1 x x v3 hss_rxclk1 x x v4 ethc_txdata[1] x x x v5 ethc_rxdata[3] x x x v6 vcc x x x v7 vcc x x x v8 v9 v10 v11 v12 v13 v14 v15 v16 v17 v18 v19 v20 vcc x x x v21 ex_data[25] x x x v22 vss x x x v23 ex_data[6] x x x v24 ex_data[8] x x x v25 ex_data[10] x x x v26 ex_data[19] x x x table 27. processors? ball map assignments (sheet 18 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no phys ical ball on package.
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 107 w1 vccp x x x w2 ethc_txdata[3] x x x w3 vss x x x w4 ethc_rxdata[2] x x x w5 ethc_crs x x x w6 ethb_col x x x w7 ethb_txdata[0] smii_txdata[0] x x x w8 w9 w10 w11 w12 w13 w14 w15 w16 w17 w18 w19 w20 ex_addr[12] x x x w21 ex_addr[6] x x x w22 ex_data[2] x x x w23 vccp x x x w24 ex_data[29] x x x w25 ex_data[31] x x x w26 ex_data[9] x x x table 27. processors? ball map assignments (sheet 19 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no physical ball on package.
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 108 document number: 306261-003 y1 ethc_txdata[2] x x x y2 ethc_txdata[0] smii_txdata[5] x x x y3 ethc_rxdata[1] x x x y4 ethc_col x x x y5 ethb_txen smii_txclk x x x y6 ethb_txdata[1] smii_txdata[1] x x config. 1 only x config. 1 only y7 vccp x x x y8 ethb_rxdata[3] smii_rxdata[3] x x config. 1 only x config. 1 only y9 vcc x x x y10 vcc x x x y11 y12 y13 y14 y15 y16 y17 vcc x x x y18 vcc x x x y19 ex_addr[13] x x x y20 ex_addr[11] x x x y21 ex_addr[10] x x x y22 ex_addr[7] x x x y23 ex_data[1] x x x y24 ex_data[4] x x x y25 ex_data[5] x x x y26 ex_data[7] x x x table 27. processors? ball map assignments (sheet 20 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no phys ical ball on package.
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 109 aa1 ethc_txclk x x x aa2 ethc_rxdata[0] smii_rxdata[5] x x x aa3 vss x x x aa4 ethb_txdata[3] smii_txdata[3] x x config. 1 only x config. 1 only aa5 vss x x x aa6 spare2 aa7 ethb_rxdv smii_rxsync x x x aa8 ethb_rxdata[1] smii_rxdata[1] x x config. 1 only x config. 1 only aa9 utp_op_data[4] etha_txen x x aa10 utp_ip_data[3] etha_rxdata[3] x x aa11 vcc x x x aa12 vcc x x x aa13 vcc x x x aa14 vcc x x x aa15 vcc x x x aa16 vcc x x x aa17 gpio[7] x x x aa18 gpio[1] x x x aa19 ssp_rxd x x x aa20 ex_addr[14] x x x aa21 vss x x x aa22 ex_addr[0] x x x aa23 ex_parity[3] x x x aa24 ex_data[26] x x x aa25 ex_data[27] x x x aa26 vss x x x table 27. processors? ball map assignments (sheet 21 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no physical ball on package.
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 110 document number: 306261-003 ab1 ethc_rxclk x x x ab2 eth_mdio x x x ab3 ethb_txdata[2] smii_txdata[2] x x config. 1 only x config. 1 only ab4 vss x x x ab5 vss x x x ab6 vss x x x ab7 ethb_rxdata[2] smii_rxdata[2] x x config. 1 only x config. 1 only ab8 utp_op_data[5] x x ab9 vss x x x ab10 utp_op_fci x x ab11 vccpll2 x x x ab12 vccpll3 x x x ab13 vcc x x x ab14 pll_lock x x x ab15 vccp x x x ab16 rxdata0 x x x ab17 gpio[12] x x x ab18 gpio[8] x x x ab19 vccp x x x ab20 i2c_sda x x x ab21 vss x x x ab22 vccp x x x ab23 ex_addr[1] x x x ab24 ex_parity[0] x x x ab25 ex_data[24] x x x ab26 ex_data[3] x x x table 27. processors? ball map assignments (sheet 22 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no phys ical ball on package.
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 111 ac1 eth_mdc x x x ac2 ethb_crs smii_sync smii_txsync x x x ac3 vccp x x x ac4 vss x x x ac5 vccp x x x ac6 utp_op_data[7] smii_txdata[4] x x ac7 utp_op_data[3] etha_txdata[3] x x ac8 utp_ip_data[5] etha_col x x ac9 utp_op_fco x x ac10 vccp x x x ac11 utp_ip_fci x x ac12 vccpll1 x x x ac13 utp_ip_addr[4] x x ac14 reset_in_n x x x ac15 jtg_tms x x x ac16 jtg_tck x x x ac17 cts0_n x x x ac18 gpio[14] x x x ac19 gpio[9] x x x ac20 gpio[4] x x x ac21 ssp_txd x x x ac22 ex_addr[15] x x x ac23 vss x x x ac24 ex_addr[9] x x x ac25 ex_data[0] x x x ac26 vccp x x x table 27. processors? ball map assignments (sheet 23 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no physical ball on package.
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 112 document number: 306261-003 ad1 ethb_txclk smii_clk x x x ad2 ethb_rxclk smii_rxclk x x x ad3 ethb_rxdata[0] smii_rxdata[0] x x x ad4 utp_ip_data[7] smii_rxdata[4] x x ad5 vccp x x x ad6 utp_ip_data[6] etha_crs x x ad7 vss x x x ad8 utp_op_soc x x ad9 utp_op_addr[3] x x ad10 utp_ip_soc x x ad11 osc_vccp x x x ad12 osc_vss x x x ad13 osc_vcc x x x ad14 utp_ip_addr[0] x x ad15 vss x x x ad16 jtg_tdi x x x ad17 txdata1 x x x ad18 txdata0 x x x ad19 vss x x x ad20 gpio[13] x x x ad21 gpio[5] x x x ad22 gpio[0] x x x ad23 ssp_sfrm x x x ad24 i2c_scl x x x ad25 ex_addr[16] x x x ad26 ex_addr[8] x x x table 27. processors? ball map assignments (sheet 24 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no phys ical ball on package.
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 113 ae1 vss x x x ae2 utp_op_data[6] x x ae3 utp_op_data[2] etha_txdata[2] x x ae4 utp_op_data[1] etha_txdata[1] x x ae5 utp_ip_data[4] etha_rxdv x x ae6 utp_ip_data[1] etha_rxdata[1] x x ae7 vccp x x x ae8 utp_op_addr[4] x x ae9 utp_op_addr[1] x x ae10 utp_ip_fco x x ae11 osc_vssp x x x ae12 osc_vssp x x x ae13 utp_ip_addr[3] x x ae14 utp_ip_addr[1] x x ae15 vccp x x x ae16 scantestmode_n x x x ae17 jtg_tdo x x x ae18 rxdata1 x x x ae19 rts1_n x x x ae20 rts0_n x x x ae21 gpio[15] x x x ae22 gpio[6] x x x ae23 gpio[2] x x x ae24 ssp_sclk x x x ae25 ssp_extclk x x x ae26 vss x x x table 27. processors? ball map assignments (sheet 25 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no physical ball on package.
package information august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 114 document number: 306261-003 4.4 package thermal specifications the thermal parameters defined in table 28 , table 29 , and table 30 are based on simulated results of packages assembled on standard multi-layer, 2s2p, 1.0-oz copper layer boards in a natural convection environment. the maximum case temp erature is based on the maximum junction temperature and defined by the relationship: t case max = t jmax - ( jt x power) af1 vss x x x af2 vss x x x af3 utp_op_data[0] etha_txdata[0] x x af4 utp_ip_data[2] etha_rxdata[2] x x af5 vss x x x af6 utp_ip_data[0] etha_rxdata[0] x x af7 utp_op_clk etha_txclk x x af8 utp_op_addr[2] x x af9 utp_op_addr[0] x x af10 utp_ip_clk etha_rxclk x x af11 osc_in x x x af12 vccp x x x af13 osc_out x x x af14 utp_ip_addr[2] x x af15 bypass_clk x x x af16 pwron_reset_n x x x af17 highz_n x x x af18 jtg_trst_n x x x af19 vccp x x x af20 cts1_n x x x af21 vss x x x af22 gpio[11] x x x af23 gpio[10] x x x af24 gpio[3] x x x af25 vss x x x af26 vss x x x table 27. processors? ball map assignments (sheet 26 of 26) ball signal name processor number configuration 1 configuration 2 configuration 3 intel ? ixp465 intel ? ixp460 intel ? ixp455 note: interfaces not being utilized at a system le vel may require external pull-up or pull- down resistors. for specific details and requirements, see section 4.2, ?functional si gnal definitions? on page 46 . note: configuration 1,2 and 3 are set by the expans ion bus configuration when reset is deasserted. blank field indicates no phys ical ball on package.
package information intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 115 where jt is the junction-to-package top thermal characterization parameter. if the case temperature exceeds the specified t case max, thermal enhancements such as heat sinks or forced air will be required. in the tables below, ja is the package junction- to-air thermal resistance. table 28. 2.8-watt maximum power dissipation package type estimated power (tpd) ja jt t case max. ? 35mm hsbga 2.8w 12.5 c/w 1.4 c/w 116 c ? this is the maximum allowable case te mperature and not normal operating condition. table 29. 3.3-watt maximum power dissipation package type estimated power (tpd) ja jt t case max. ? 35mm hsbga 3.3w 12.5 c/w 1.4 c/w 115 c ? this is the maximum allowable case te mperature and not normal operating condition. table 30. 4.0-watt maximum power dissipation package type estimated power (tpd) ja jt t case max. ? 35mm hsbga 4.0w 12.5 c/w 1.4 c/w 114 c ? this is the maximum allowable case te mperature and not normal operating condition.
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 116 document number: 306261-003 5.0 electrical specifications 5.1 absolute maximum ratings warning: stressing the device beyond the absolute maximu m ratings may cuse permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating condi tions may affect device reliability. 5.2 v ccpll1 , v ccpll2 , v ccpll3 , osc_vccp, osc_vcc pin requirements to reduce voltage-supply noise on the analog sec tions of the ixp45x/ixp 46x network processors, the phase-lock loop circuits (v ccpll1 , v ccpll2 , v ccpll3 ) and oscillator circuit (osc_vcc, osc_vccp) require isolated voltage supplies. the filter circuits for each supply ar e shown in the following sections. 5.2.1 v ccpll1 requirement a parallel combination of a 10-nf capacitor (for by pass) and a 200-nf capacitor (for a first-order filter with a cut-off frequency below 30 mhz) must be connected to the v ccpll1 pin of the ixp45x/ixp46x network processors. the ground of both capacitors should be connected to the nearest v ss supply pin. both capacitors should be located less than 0.5 inch away from the v ccpll1 pin and the associated v ss pin. in order to achieve the 200-nf capacitance, a para llel combination of two 100-nf capacitors may be used as long as the capacitors ar e placed directly beside each other. parameter maximum rating ambient air temperature (extended) -40o c to 85o c ambient air temperature (commercial) 0o c to 70o c supply voltage core -0.3 v to 2.1 v supply voltage i/o -0.3 v to 3.6 v supply voltage ddr -0.3v to 2.75v supply voltage oscillator (osc_vcc) -0.3 v to 2.1 v supply voltage oscillator (osc_vccp) -0.3 v to 3.6 v supply voltage pll (v ccpll1 ) -0.3 v to 2.1 v supply voltage pll (v ccpll2 ) -0.3 v to 2.1 v supply voltage pll (v ccpll3 ) -0.3 v to 2.1 v voltage on any i/o ball -0.3 v to 3.6v storage temperature -55 o c to 125 o c
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 117 5.2.2 v ccpll2 requirement a parallel combination of a 10 -nf capacitor (for bypass) and a 200-nf capacitor (for a first-order filter with a cut-off frequency below 30 mhz) must be connected to the v ccpll2 pin of the ixp45x/ixp46x network processors. the ground of both capacitors should be connected to the nearest v ss supply pin. both capacitors should be located less than 0.5 inch away from the v ccpll2 pin and the associated v ss pin. in order to achieve the 200-nf capacitance, a parall el combination of two 100-nf capacitors may be used as long as the capacitors are placed directly beside each other. 5.2.3 v ccpll3 requirement a parallel combination of a 10 -nf capacitor (for bypass) and a 200-nf capacitor (for a first-order filter with a cut-off frequency below 30 mhz) must be connected to the v ccpll3 pin of the ixp45x/ixp46x network processors. the ground of both capacitors should be connected to the nearest v ss supply pin. both capacitors should be located less than 0.5 inch away from the v ccpll3 pin and the associated v ss pin. in order to achieve the 200-nf capacitance, a parall el combination of two 100-nf capacitors may be used as long as the capacitors are placed directly beside each other. figure 9. v ccpll1 power filtering diagram vcc in te l ? ixp45x/ixp46x network processors 10 nf v ss v ccpll1 100 nf 100 nf v ss figure 10. v ccpll2 power filtering diagram vcc 10 nf v ss v ccpll2 100 nf 100 nf v ss in te l ? ixp45x/ixp46x network processors
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 118 document number: 306261-003 5.2.4 osc_vccp requirement a single, 170-nf capacitor must be connected between the osc_vccp pin and osc_vssp pin of the ixp45x/ixp46x network processors. this cap acitor value provides both bypass and filtering. when 170 nf is an inconvenient size, capacitor va lues between 150 nf to 20 0 nf can be used with little adverse effects, a ssuming that the effective series resist ance of the 200-nf capacitor is under 50 m ? .. in order to achieve a 200-nf cap acitance, a parallel combination of two 100-nf capacitors may be used as long as the capacitors are placed directly beside each other. osc_vssp is made up with two pins, ad10 and af10. ensure that both pins are connected as shown in figure 12 . 5.2.5 osc_vcc requirement a parallel combination of a 10-nf capacitor (for by pass) and a 200-nf capacitor (for a first-order filter with a cut-off frequency below 33 mhz) must be connected to both of the osc_vcc pins of the ixp45x/ixp46x network processors. the grounds of both capacitors should be connected to the osc_vss supply pin. both capacitors should be located less than 0.5 inch away fr om the osc_vcc pin and the associated osc_vss pin. in order to achieve a 200-nf cap acitance, a parallel combination of two 100-nf capacitors may be used as long as the capacitors ar e placed directly beside each other. figure 11. v ccpll3 power filtering diagram vcc in te l ? ixp45x/ixp46x network processors 10 nf v ss v ccpll3 100 nf 100 nf v ss figure 12. osc_vccp power filtering diagram vccp 170 nf v ss osc_vccp in te l ? ixp45x/ixp46x network processors osc_vssp osc_vssp
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 119 5.3 rcomp pin requirements figure 14 shows the requiremen ts for the rcomp pin. figure 13. osc_vcc power filtering diagram vcc 10 nf v ss 100 nf 100 nf osc_vcc intel ? ix p 45x /ix p 46 x network processors osc_vss figure 14. rcomp pin external resistor requirements b5030-01 v ss rcomp v ss 34 ? , + 1% intel ? ixp45x/ixp46x network processors
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 120 document number: 306261-003 5.4 ddri_rcomp pin requirements figure 15 shows the requirements for the ddri_rcomp pin. 5.5 dc specifications 5.5.1 operating conditions figure 15. ddri_rcomp pin external resistor requirements table 31. operating conditions symbol parameter min. typ. max. units v ccp voltage supplied to the i/o, with the exception of the ddri sdram interface. 3.135 3.3 3.465 v v cc voltage supplied to the internal logic. for 266, 400, and 533 mhz for 667 mhz 1.235 1.425 1.3 1.5 1.365 1.575 v v v ccm voltage supplied to the ddri sdram interface. 2.300 2.5 2.700 v osc_vcc voltage supplied to the internal oscillator logic. for 266, 400, and 533 mhz for 667 mhz 1.235 1.425 1.3 1.5 1.365 1.575 v osc_vccp voltage supplied to the oscillator i/o. 3.135 3.3 3.465 v v ccpll1 voltage supplied to the analog phase-lock loop. for 266, 400, and 533 mhz for 667 mhz 1.235 1.425 1.3 1.5 1.365 1.575 v v ccpll2 voltage supplied to the analog phase-lock loop. for 266, 400, and 533 mhz for 667 mhz 1.235 1.425 1.3 1.5 1.365 1.575 v v ccpll3 voltage supplied to the analog phase-lock loop. for 266, 400, and 533 mhz for 667 mhz 1.235 1.425 1.3 1.5 1.365 1.575 v b5031-01 v ss ddr1_rcomp v ss 20 ? , + 1% intel ? ixp45x/ixp46x network processors
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 121 5.5.2 pci dc parameters 5.5.3 usb 1.1 dc parameters table 32. pci dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 0.5 v ccp v 3 , 4 v il input-low voltage 0.3 v ccp v 3 v oh output-high voltage i out = -500 a 0.9 v ccp v 3 v ol output-low voltage i out = 1500 a 0.1 v ccp v 3 i il input-leakage current 0 < v in < v ccp -10 10 a 1 , 3 c in input-pin capacitance 5 pf 2 , 3 c out i/o or output pin capacitance 5pf 2 , 3 c idsel idsel-pin capacitance 5 pf 2 , 3 l pin pin inductance 20 nh 2 , 3 notes: 1. input leakage currents include hi-z output leakage fo r all bidirectional buffers with tri-state outputs. 2. these values are typical values seen by the manufacturing process and are not tested. 3. for additional information, see the pci local bus specification , revision 2.2. 4. please consult the intel ? ixp4xx product line of network processors specification update for the vih specification. table 33. usb 1.1 dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v 1 v il input-low voltage 0.8 v v oh output-high voltage i out = -6.1 * v oh ma 2.8 v v ol output-low voltage iout = 6.1 * v oh ma 0.3 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 2 notes: 1. please consult the product specificat ion update for the vih specification. 2. these values are typical va lues seen by the manufacturi ng process and are not tested.
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 122 document number: 306261-003 5.5.4 utopia level 2 dc parameters 5.5.5 mii/smii dc parameters table 34. utopia level 2 dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -8 ma 2.4 v v ol output-low voltage i out = 8 ma 0.5 v i oh output current at high voltage v oh > 2.4 v -8 ma i ol output current at low voltage v ol < 0.5 v 8 ma i il input-leakage current 0 < v in < v ccp -10 10 a 1 c in input-pin capacitance 5 pf 2 c out i/o or output pin capacitance 5pf 2 notes: 1. input leakage currents include hi-z output leakage for all bidirectional buffers with tri-state outputs. 2. these values are typical values seen by the manufacturing process and are not tested. table 35. mii/smii dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v ohmii output-high voltage i out = - 6 ma 2.4 v v olmii output-low voltage i out = 6 ma 0.4 v v ohsmii output-high voltage i out = -10 ma 2.4 v v olsmii output-low voltage i out = 10ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 notes: 1. these values are typical values seen by the manufacturing process and are not tested.
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 123 5.5.6 mdi dc parameters 5.5.7 ddri sdram bus dc parameters table 36. mdi dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = - 6 ma 2.4 v v ol output-low voltage i out = 6 ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 c inmdio input-pin capacitance 5 pf 1 notes: 1. these values are typical va lues seen by the manufacturi ng process and are not tested. table 37. ddri sdram bus dc parameters symbol parameter conditions min. typ. max. units notes v ddri_vref i/o reference voltage 0.49*v ccm 0.51*v ccm v v ih input-high voltage v ddri_vref + 0.15 v ccm +0.3 v 1 v il input-low voltage -0.3 v ddri_vref - 0.15 v 2 v oh output-high voltage i out = -15ma 1.95 v v ol output-low voltage i out = 15ma 0.35 v i il input-leakage current 0 < v in < v ccm -10 10 a c io i/o-pin capacitance 5 pf 1 notes: 1. these values are typical values seen by the manufacturing process and are not tested. 2. only 2.5v ddri sdram is supported
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 124 document number: 306261-003 5.5.8 expansion bus dc parameters 5.5.9 high-speed, serial interface 0 dc parameters table 38. expansion bus dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v ohdrv0 output-high voltage i out = -8 ma 2.4 v 1 , 2 v oldrv0 output-low voltage i out = 8 ma 0.4 v 1 , 2 v ohdrv1 output-high voltage i out = -14 ma 2.4 v 1 , 3 v oldrv1 output-low voltage i out = 14ma 0.4 v 1 , 3 v ohdrv2 output-high voltage i out = -20 ma 2.4 v 1 , 4 v oldrv2 output-low voltage i out = 20 ma 0.4 v 1 , 4 i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 2 notes: 1. these values are typical values seen by the manufacturing process and are not tested. 2. the values represented with this voltage paramete r would typically be used in a system in which the expansion bus interfaces a single load of 6pf plac ed less than 2 inches away from the ixp45x/ixp46x network processors. this drive strength setting shoul d be used to avoid ringing when minimal loading is attached. please use ibis models and si mulation tools to guarantee the design. 3. the values represented with this voltage paramete r would typically be used in a system in which the expansion bus interfaces four loads of 6pf each. all components are plac ed no further than 4 inches away from the ixp45x/ixp46x network processors. this dr ive strength setting should be used to avoid ringing when medium loading is attached. please use ibis models and simulation tools to guarantee the design. 4. the values represented with this voltage paramete r would typically be used in a system in which the expansion bus interfaces eight loads of 6pf and al l components are placed less than 6 inches from the ixp45x/ixp46x network processors. another use case of this drive strength woul d typically be four loads of 6pf operating at 80mhz. this drive strength setting should be used to av oid ringing when maximum loading or frequency is utilized. please use ibis models and simulation tools to guarantee the design. table 39. high-speed, serial interface 0 dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = - 6ma 2.4 v v ol output-low voltage i out = 6ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 notes: 1. these values are typical values seen by the manufacturing process and are not tested.
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 125 5.5.10 high-speed, serial interface 1 dc parameters 5.5.11 uart dc parameters 5.5.12 serial peripheral interface dc parameters table 40. high-speed, serial interface 1 dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -6ma 2.4 v v ol output-low voltage i out = 6ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 notes: 1. these values are typical va lues seen by the manufacturi ng process and are not tested. table 41. uart dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = - 4ma 2.4 v v ol output-low voltage i out = 4ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 notes: 1. these values are typical va lues seen by the manufacturi ng process and are not tested. 2. this interface has been designed assuming a si ngle load which can be between 5pf to 25pf. table 42. serial periphera l interface dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = - 6ma 2.4 v v ol output-low voltage i out = 6ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 notes: 1. these values are typical va lues seen by the manufacturi ng process and are not tested.
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 126 document number: 306261-003 5.5.13 i 2 c interface dc parameters 5.5.14 gpio dc parameters 5.5.15 jtag dc parameters table 43. i 2 c interface dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = n/a n/a n/a n/a v 2 v ol output-low voltage i out = 4ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 notes: 1. these values are typical values seen by the manufacturing process and are not tested. 2. voltage output high for this interface is not applicable due to it being an open drain i/o. table 44. gpio dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage for gpio 0 to gpio 13 i out = -16 ma 2.4 v v ol output-low voltage for gpio 0 to gpio 13 i out = 16 ma 0.4 v v oh output-high voltage for gpio 14 and gpio 15 i out = -4 ma 2.4 v v ol output-low voltage for gpio 14 and gpio 15 i out = 4 ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 notes: 1. these values are typical values seen by the manufacturing process and are not tested. table 45. jtag dc parameters (sheet 1 of 2) symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -4 ma 2.4 v notes: 1. these values are typical values seen by the manufacturing process and are not tested.
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 127 5.5.16 reset dc parameters 5.5.17 all remaining i/o dc parameters v ol output-low voltage i out = 4 ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 table 46. pwron_reset _n and reset_in_n parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v table 47. all remaining i/o dc parameters (jtag, pll_lock) symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = - 4ma 2.4 v v ol output-low voltage i out = 4ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 notes: 1. these values are typical va lues seen by the manufacturi ng process and are not tested. 2. these parameters are only applicable to signal other than power and ground signals. table 45. jtag dc parameters (sheet 2 of 2) symbol parameter conditions min. typ. max. units notes notes: 1. these values are typical va lues seen by the manufacturi ng process and are not tested.
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 128 document number: 306261-003 5.6 ac specifications 5.6.1 clock signal timings 5.6.1.1 processors? clock timings table 48. devices? clock timings symbol parameter min. nom. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v t frequency clock frequency for ixp45x/ixp46x network processors oscillator. 33.33 33.33 33.33 mhz 1 , 3 u frequency clock tolerance over -40o c to 85o c. -50 50 ppm c in pin capacitance of ixp45x/ixp46x network processors inputs. 5pf t dc duty cycle 35 50 65 % 2 notes: 1. this value is oscillator input. us e as an oscillator input, tie to the crystal input pin and leave the crystal output pin disconnected. 2. this parameter applies when driving the clock input with an oscillator. 3. where the ixp45x/ixp46x network processors are config ured with an input reference-clock, the slew rate should never be faster than 2.5 v/ns to ensure prop er pll operation. to properly guarantee pll operation at the slower slew rate, the vih and vil levels need to be met at the 33.33mhz frequency. table 49. processors? clock timings spread spectrum parameters spread-spectrum conditions min max notes frequency deviation from 33.33 mhz as a percentage -2.0% +0.0% characterized and guaranteed by design, but not tested. do not over-clock the pll input. the a.c. timings will not be guaranteed if the device exceeds 33.33 mhz. modulation frequency 50 khz characterized and guaranteed by design, but not tested notes: 1. it is important to note that when using spread spectr um clocking, other clocks in the system will change frequency over a specific range. this change in other clocks can present some s ystem level limitations. please refer to the application note titled spread spectrum clocking to reduce emi application note , when designing a product that util izes spread spectrum clocking.
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 129 5.6.1.2 pci clock timings 5.6.1.3 mii/smii clock timings figure 16. typical connection to an oscillator table 50. pci clock timings symbol parameter 33 mhz 66 mhz units notes min. max. min. max. t periodpciclk clock period for pci clock 30 15 ns t clkhigh pci clock high time 11 6 ns t clklow pci clock low time 11 6 ns t slew rate slew rate requirements for pci clock 1 4 1.5 4 v/ns table 51. mii/smii clock timings (sheet 1 of 2) symbol parameter min. nom. max. units notes t period100mbit clock period for smii_clk reference clock when operating in smii or source synchronous mode of operation 88ns t period100mbit clock period for smii_txclk and smii_rxclk clock when operating in source synchronous smii mode of operation 88ns t period100mbit clock period for tx and rx ethernet clocks 40 40 ns intel? ix p 45x / ix p 46x network processors oscillator osc_in osc_out
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 130 document number: 306261-003 5.6.1.4 utopia level 2 clock timings 5.6.1.5 expansion bus clock timings t period10mbit clock period for tx and rx ethernet clocks 400 400 ns t duty duty cycle for tx and rx ethernet clocks 35 50 65 % frequency tolerance frequency tolerance requirement for tx and rx ethernet clocks +/- 50 +/- 100 ppm table 52. utopia level 2 clock timings symbol parameter min. nom. max. units notes t period clock period for tx and rx utopia level 2 clocks 30.303 ns t duty duty cycle for tx and rx utopia level 2 clocks 40 50 60 % t rise/fall rise and fall time requirements for tx and rx utopia level 2 clocks 2ns table 53. expansion bus clock timings symbol parameter min. nom. max. units notes t period clock period for expansion bus clock 12.5 ns t duty duty cycle for expans ion bus clock 40 50 60 % t rise/fall rise and fall time requirements for expansion bus clock 2ns table 51. mii/smii clock timings (sheet 2 of 2) symbol parameter min. nom. max. units notes
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 131 5.6.2 bus signal timings the ac timing waveforms are shown in the following sections. 5.6.2.1 pci figure 17. pci output timing note: v hi = 0.6 v cc and v low = 0.2 v cc. figure 18. pci input timing a9572-01 clk output delay t clk2out(b) v low v hi a9573-01 clk input inputs valid t hold t setup(b)
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 132 document number: 306261-003 5.6.2.2 usb 1.1 interface for timing parameters, see the usb 1.1 specifi cation. the usb 1.1 in terface for the ixp45x/ ixp46x network processors supports both a devi ce or function controller only and a host only controller. the ixp45x/ixp46x network proces sors usb 1.1 device interface cannot be line- powered. to assure proper operation with the ixp45x/ixp46x network pr ocessors usb interfaces, please consult the intel? ixp45x and intel? ixp46x product li ne of network processors hardware design guidelines and the intel ? ixp4xx product line of network processors specification update . table 54. pci bus signal timings symbol parameter 33 mhz 66 mhz units notes min. max. min. max. t clk2outb clock to output for all bused signals. this is the pci_ad[31:0], pci_cbe_n [3:0], pci_par, pci_frame_n, pci_irdy_n, pci_trdy_n, pci_stop_n, pci_devsel_n, pci_perr_n, pci_serr_n 2111 6ns 1 , 2 , 5 , 7 , 8 t clk2out clock to output for all point-to-point signals. this is the pci_gnt_n and pci_req_n(0) only. 2121 6ns 1 , 2 , 5 , 7 , 8 t setupb input setup time for all bused signals. this is the pci_ad[31:0], pci_cbe_n [3:0], pci_par, pci_frame_n, pci_irdy_n, pci_trdy_n, pci_stop_n, pci_devsel_n, pci_perr_n, pci_serr_n 73ns 4 , 6 , 7 , 8 t setup input setup time for all point-to- point signals. this is the pci_req_n and pci_gnt_n(0) only. 10, 12 5 ns 3 , 4 , 7 , 8 t hold input hold time from clock. 0 0 ns 4 , 7 , 8 t rst-off reset active-to-output float delay 40 40 ns 5 , 6 , 7 , 8 notes: 1. see the timing measurement conditions. 2. parts compliant to the 3.3 v signaling environment. 3. req# and gnt# are point-to-point signals and have di fferent output valid delay and input setup times than do bused signals. gnt# has a setup of 10 ns for 33 mhz and 5 ns for 66 mhz; req# has a setup of 12 ns for 33 mhz and 5 ns for 66 mhz. 4. rst# is asserted and de-asserted as ynchronously with respect to clk. 5. all pci outputs must be asynchronously driven to a tri-state value when rst# is active. 6. setup time applies only when the device is not drivi ng the pin. devices cannot drive and receive signals at the same time. 7. timing was tested with a 70-pf capacitor to ground. 8. for additional information, see the pci local bus specification , revision 2.2.
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 133 5.6.2.3 utopia level 2 figure 19. utopia level 2 input timings table 55. utopia level 2 input timings values symbol parameter min. max. units notes t setup input setup prior to rising edge of clock. inputs included in this timing are utp_ip_data[7:0], utp_ip_soc, and utp_ip_fci, and utp_op_fci. 8ns t hold input hold time after the rising edge of the clock. inputs included in this timing are utp_ip_data[7:0], utp_ip_soc, and utp_ip_fci, and utp_op_fci. 1ns figure 20. utopia level 2 output timings a9578-01 thold tsetup clock signals a9579-01 tclk2out tholdout clock signals
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 134 document number: 306261-003 5.6.2.4 mii/smii table 56. utopia level 2 output timings values symbol parameter min. max. units notes t clk2out rising edge of clock to signal output. outputs included in this timing are utp_op_soc, utp_op_fco, utp_ip_fco, utp_op_data[7:0], utp_ip_addr[4:0] and utp_op_addr[4:0]. 17 ns 1 t holdout signal output hold time after the rising edge of the clock. outputs included in this timing are utp_op_soc, utp_op_fco, utp_ip_fco, utp_op_data[7:0], utp_ip_addr[4:0] and utp_op_addr[4:0]. 1ns 1 notes: 1. timing was designed for a system load between 5pf and 25pf figure 21. smii output timings table 57. smii output timings values symbol parameter min. max. units notes t 1 clock to output delay for smii_txd[4:0] and smii_sync with respect to rising edge of smii_clk 1.5 5 ns 1 t 2 smii_txd[4:0] and smii_sync hold time after smii_clk. 1.5 ns 1 notes: 1. timing was designed for a system load between 5pf and 15pf smii_clk smii_outputs t 1 t 2
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 135 figure 22. smii input timings table 58. smii input timings values symbol parameter min. max. units notes t 3 smii_rxd setup time prior to rising edge of smii_clk 1.5 ns t 4 smii_rxd hold time after the rising edge of smii_clk 1ns figure 23. source synchronous smii output timings table 59. source synchronous smii output timings values symbol parameter min. max. units notes t 1 clock to output delay for smii_txd[4:0] and smii_txsync with respect to rising edge of smii_txclk 1.5 5 ns 1 t 2 smii_txd[4:0] and smii_txsync hold time after smii_txclk. 1.5 ns 1 notes: 1. timing was designed for a system load between 5pf and 15pf smii_clk smii_inputs t 3 t 4 smii_txclk smii_outputs t 1 t 2
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 136 document number: 306261-003 figure 24. source synchronous smii input timings table 60. source synchronous smii input timings values symbol parameter min. max. units notes t 3 smii_rxd and smii_rxsync setup time prior to rising edge of smii_rxclk 1.5 ns 1 t 4 smii_rxd and smii_rxsync hold time after the rising edge of smii_clk 1ns 1 notes: 1. timing was designed for a system load between 5pf and 15pf figure 25. mii output timings table 61. mii output timings values symbol parameter min. max. units notes t 1 clock to output delay for eth_txdata and eth_txen. 12.5 ns 1 , 2 t 2 eth_txdata and eth_txen hold time after eth_txclk. 1.5 ns 2 notes: 1. these values satisfy t the mii specification re quirement of 0 ns to 25 ns clock to output delay. 2. timing was designed for a system load between 5 pf and 15 pf. smii_rxclk smii_inputs t 3 t 4 a9580-01 eth_tx_clk eth_tx_data[7:0] eth_tx_en eth_crs t 1 t 2
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 137 5.6.2.5 mdio figure 26. mii input timings table 62. mii input timings values symbol parameter min. max. units notes t 3 eth_rxdata and eth_rxdv setup time prior to rising edge of eth_rxclk 5.5 ns 1 t 4 eth_rxdata and eth_rxdv hold time after the rising edge of eth_rxclk 0 ns 1 , 2 notes: 1. these values satisfying the 10-ns setup and hold time requirements nec essary for the mii specification. 2. the t4 input hold timing parameter is not 100% tested and is guaranteed by design. figure 27. mdio output timings note: processor is sourcing mdio. a9581-01 eth_rx_clk eth_rx_data[7:0] eth_rx_dv eth_crs t 4 t 3 a9582-02 eth_mdc eth_mdio t 1 t 2
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 138 document number: 306261-003 5.6.2.6 ddri sdram bus figure 28. mdio input timings note: phy is sourcing mdio. table 63. mdio timings values symbol parameter min. max. units notes t1 eth_mdio, clock to output timing with respect to rising edge of eth_mdc clock eth_mdc/2 + 15 ns ns t2 eth_mdio output hold timing after the rising edge of eth_mdc clock 10 ns t3 eth_mdio input setup prior to rising edge of eth_mdc clock 3 ns t4 eth_mdio hold time after the rising edge of eth_mdc clock 1 ns t5 eth_mdc clock period 125 500 ns 1 note: 1. timing was designed for a system load between 5pf and 20pf figure 29. ddri sdram write timings a9583-02 eth_mdc eth_mdio t 3 t 5 t 4 ddri_m_clk addr/ctrl t 4 ddri_dqs ddri_dq, _cb, _dm t 3 t 2 t 1 t 5 t 6 addr/cmd valid dat a valid
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 139 table 64. ddri sdram write timings values symbol parameter min. max. units notes t 1 output valid for ddri_dqs prior to each edge of ddri_m_clk. 1.4 ns 1 t 2 ddri_dqs output hold time after each edge of the ddri_m_clk. 1.0 ns 1 t 3 output valid for addr/ctrl prior to the rising edge of ddri_m_clk. address and control signals consist of ddri_ras_n, ddri_cas_n, ddri_cs_n, ddri_we_n, ddri_ba, ddri_ma, and ddri_cke. 2.5 ns 1 t 4 addr/ctrl output hold time after the rising edge of the ddri_m_clk. address and control signals consist of ddri_ras_n, ddri_cas_n, ddri_cs_n, ddri_we_n, ddri_ba, ddri_ma, and ddri_cke. 2.3 ns 1 t 5 output valid for ddri_dq, ddri_cb, and ddri_dm prior to each edge of ddri_dqs. 1.0 ns t 6 ddri_dq, ddri_cb, and ddri_dm output hold time after each edge of the ddri_dqs. 1.0 ns notes: 1. ddri_m_clk is representative of all ddri _ck and ddri_ck_n signals. the rising edge of ddri_m_clk represents the crossover point of the respective ddri_ck and ddri_ck_n signals. the skew between the separate ddr clocks have been compensated in the timings which have been described. the period to period clock jitter on each ddri_m_clk pair is spec?ed at +/-100ps. figure 30. ddri sdram read timings (2.0 cas latency) ddri_m_clk ddri_dqs t 1 ddri_rcvenout_n ddri_rcvenin_n ddri_dq, _cb, _dm rd cmd d0 d1 d2 d3 d4 d5 d6 d7 t 3 t 2 t 4 t 5 t 6
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 140 document number: 306261-003 figure 31. ddri sdram read timings (2.5 cas latency) table 65. ddri sdram read timing values symbol parameter min. max. units notes t 1 ddri_rcvenout_n minimum output valid time after ddri_m_clk 0.9 ns 1 t 2 ddri_rcvenout_n maximum output valid time after ddri_m_clk 2.7 ns 1 t 3 ddri_rcvenin_n input valid time before ddri_dqs 3.6 ns t 4 ddri_rcvenin_n hold time from ddri_dqs valid -0.1 ns t 5 maximum delay for data valid after any edge of ddri_dqs. both of these signal are inputs from the memory during read operations. 0.75 ns t 6 maximum guaranteed time before data begins to transition to the next valid data prior to any ddri_dqs clock edge. both of these signal are inputs from the memory during read operations. this time in conjunction with timing parameter t 5 specify the window for which the ddri data signals can operate with the memory controller on the ixp45x/ixp46x network processors. 1.0 ns notes: 1. designed to jedec specification, it is recommended that ibis models be used to verify signal integrity on individual designs ddri_m_clk ddri_dqs t 1 ddri_rcvenout_n ddri_rcvenin_n ddri_dq, _cb, _dm rd cmd d0 d1 d2 d3 d4 d5 d6 d7 t 3 t 2 t 4 t 5 t 6
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 141 5.6.2.7 expansion bus 5.6.2.7.1 expansion bus synchronous operation figure 32. expansion bus synchronous timing table 66. expansion bus synchronous operation timing values symbol parameter low drive med drive hi drive units notes min. max. min. max. min. max. t 1 valid rising edge of ex_clk to valid signal on the output. 10 8.5 6.5 ns 1 , 2 , 3 , 4 t 2 valid signal hold time after the rising edge of ex_clk 1 1 1 ns 1 , 2 , 3 , 4 t 3 valid data signal on an input prior to the rising edge of ex_clk 222ns 1 , 2 , 3 , 4 t 4 required hold time of a dat a input after the rising edge of ex_clk 0.5 0.5 0.5 ns 1 , 2 , 3 , 4 t 5 valid control/arbiter signal on an input prior to the rising edge of ex_clk 3.5 3.5 3.5 ns 1 , 2 , 3 , 4 t 6 required hold time of a control/arbiter input after the rising edge of ex_clk 0.5 0.5 0.5 ns 1 , 2 , 3 , 4 notes: 1. timing was designed for a system load between 5pf and 60pf for low drive setting at typically no more than a 33mhz clock 2. timing was designed for a system load between 5pf and 50pf fo r medium drive setting at typically no more than a 66mhz clock 3. timing was designed for a system load between 5pf and 40pf for high drive setting at typically no more than a 80mhz clock 4. drive settings do not apply to ex_cs_n signa ls and are expected to be point to poin t. the timing on this signal was designed for a system load between 5pf and 10pf 5. ex_control_signals output signals consist of ex_ale, ex_addr, ex_cs_n, ex_gnt_req_n, ex_gnt_n, ex_rd_n, ex_wr_n, ex_wait_n 6. ex_control_signals input signals consist of ex_add r, ex_cs_n, ex_slave_cs_n, ex_req_gnt_n, ex_req_n, ex_burst, ex_rd_n, ex_wr_n ex_clk t 4 t 3 t 2 t 1 ex_data, _be_n, parity - output_signals ex_ control signals - output_signals t 6 t 5 ex_data, _be_n, parity - input_signals ex_ control signals - input_signals
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 142 document number: 306261-003 5.6.2.7.2 expansion bus asynchronous operation figure 33. intel multiplexed mode table 67. intel multiplexed mode values (sheet 1 of 2) symbol parameter min. max. units notes talepulse pulse width of ale (addr is valid at the rising edge of ale) 1 4 cycles 1 , 7 tale2addrhold valid address hold time after from falling edge of ale 1 1 cycles 1 , 2 , 7 tdval2valwrt write data valid prior to wr_n falling edge 1 4 cycles 3 , 7 twrpulse pulse width of the wr_n 1 16 cycles 4 , 7 tdholdafterwr valid data after the rising edge of wr_n 1 4 cycles 5 , 7 tale2valcs valid chip select afte r the falling edge of ale 1 4 cycles 7 notes: 1. the ex_ale signal is extended form t to 4t nnsec based on the programming of the t1 timing parameter. the parameter tale2addrhold is fixed at t. 2. setting the address phase pa rameter (t1) will adjust the duration that th e address appears to the external device. 3. setting the data setup phase parameter (t2) will adj ust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. setting the data strobe phase parameter (t3) will adjust the duration that the data strobe appears (read or write) to an external device. data will be available during this time as well. 5. setting the data hold strobe phase parameter (t4) will adjust the duration that the chip selects, address, and data (during a write) will be held. 6. setting the recovery phase parameter (t5) will adj ust the duration between successive accesses on the expansion interface. 7. t is the period of the clock measured in ns. 8. clock to output delay fo r all signals will be a maximum of 15 ns for devices r equiring operation in synchronous mode. 9. timing was designed for a system load between 5pf and 60pf for high drive setting a9585-01 ex_clk ex_addr ex_data ex_rd_n ex_data ex_ale ex_wr_n ex_cs_n valid address t5 1-16 cycles t4 1-4 cycles t recov t ale2addrhold t rdsetup t rdhold t dval2valwrt t dhold2afterwr t3 1-16 cycles t2 1-4 cycles t1 2-5 cycles ale extended t alepulse t ale2valcs t wrpulse address output data address input data multiplexed address/data
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 143 trdsetup data valid required before the rising edge of rd_n 5.3 14.7 ns trdhold data hold required after the rising edge of rd_n 2 ns trecov time needed between successive accesses on expansion interface. 1 16 cycles 6 figure 34. intel simplex mode table 67. intel multiplexed mo de values (sheet 2 of 2) symbol parameter min. max. units notes notes: 1. the ex_ale signal is extended form t to 4t nnsec based on the programming of the t1 timing parameter. the parameter tale2addrhold is fixed at t. 2. setting the address phase para meter (t1) will adjust the du ration that the ad dress appears to t he external device. 3. setting the data setup phase parameter (t2) will adjust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. setting the data strobe phase parameter (t3) will adjust the duration that the data strobe appears (read or write) to an external device. data wi ll be available during this time as well. 5. setting the data hold strobe phase parameter (t4) will adj ust the duration that the chip selects, address, and data (during a write) will be held. 6. setting the recovery phase parameter (t5) will adjus t the duration between succ essive accesses on the expansion interface. 7. t is the period of the clock measured in ns. 8. clock to output delay for all si gnals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. timing was designed for a system load between 5pf and 60pf for high drive setting a9586-01 ex_clk ex_addr ex_data ex_rd_n ex_data ex_wr_n valid address output data t5 1-16 cycles t4 1-4 cycles ex_cs_n t wrpulse t recov t addr2valcs t dval2valwrt input data t dhold2afterwr t3 1-16 cycles t2 1-4 cycles t1 1-4 cycles t rdsetup t rdhold
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 144 document number: 306261-003 table 68. intel simplex mode values symbol parameter min. max. units notes t addr2valcs valid address to valid chip select 1 4 cycles 1 , 2 , 7 t dval2valwrt write data valid prior to expb_io_write_n falling edge 1 4 cycles 3 , 7 t wrpulse pulse width of the exp_io_write_n 1 16 cycles 4 , 7 t dholdafterwr valid data after the rising edge of expb_io_write_n 1 4 cycles 5 , 7 t rdsetup data valid required before the rising edge of exp_io_read_n 5.3 14.7 ns t rdhold data hold required after the rising edge of exp_io_read_n 2ns t recov time required between successive accesses on the expansion interface. 1 16 cycles 6 notes: 1. ex_ale is not valid in simplex mode of operation. 2. setting the address phase parameter (t1) will adjust t he duration that the address appears to the external device. 3. setting the data setup phase parameter (t2) will adjust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. setting the data strobe phase parameter (t3) will adj ust the duration that the data strobe appears (read or write) to an external device. data will be available during th is time as well. 5. setting the data hold strobe phase parameter (t4) will adjust the duration that the chip selects, address, and data (during a write) will be held. 6. setting the recovery phase parameter (t5) will adj ust the duration between successive accesses on the expansion interface. 7. t is the period of the clock measured in ns. 8. clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. timing was designed for a system load between 5pf and 60pf for high drive setting
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 145 figure 35. motorola* multiplexed mode table 69. motorola* multiplexed mode values (sheet 1 of 2) symbol parameter min. max. units notes t alepulse pulse width of ale (addr is valid at the rising edge of ale) 1 4 cycles 1 , 7 t ale2addrhold valid address hold time after from falling edge of ale 1 1 cycles 1 , 2 , 7 t dval2valds write data valid prior to exp_mot_ds_n falling edge 1 4 cycles 3 , 7 notes: 1. the ex_ale signal is extended form t to 4t nnsec, based on the programming of the t1 timing parameter. the parameter tale2addrhold is fixed at t. 2. setting the address phase parameter (t1) will adjust th e duration that t he address appears to the external device. 3. setting the data setup phase parameter (t2) will adjust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. setting the data strobe phase parameter (t3) will adjust the duration that the data strobe appears (read or write) to an external device. data wi ll be available during this time as well. 5. setting the data hold strobe phase parameter (t4) will ad just the duration that the chip selects, address, and data (during a write) will be held. 6. setting the recovery phase parameter (t5) will adjus t the duration between succ essive accesses on the expansion interface. 7. t is the period of the clock measured in ns. 8. clock to output delay for all si gnals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. timing was designed for a system load between 5pf and 60pf for high drive setting a9587-01 ex_clk ex_addr ex_data ex_rd_n (exp_mot_rnw) ex_wr_n (exp_mot_ds_n) ex_data ex_ale valid address t5 1-16 cycles t4 1-4 cycles ex_cs_n t recov t ale2addrhold t dval2valds ex_wr_n (exp_mot_ds_n) ex_rd_n (exp_mot_rnw) t dhold2afterds t3 1-16 cycles t2 1-4 cycles t1 2-5 cycles ale extended t alepulse t ale2valcs t dspulse address output data address input data multiplexed address/data t rdsetup t rdhold
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 146 document number: 306261-003 t dspulse pulse width of the exp_mot_ds_n 1 16 cycles 4 , 7 t dholdafterds valid data after the rising edge of exp_mot_ds_n 1 4 cycles 5 , 7 t ale2valcs valid chip select after the falling edge of ale 1 4 cycles 7 t rdsetup data valid required before the rising edge of exp_mot_ds_n 5.3 14.7 ns t rdhold data hold required after the rising edge of exp_mot_ds_n 2 ns t recov time needed between successive accesses on expansion interface. 116cycles 6 table 69. motorola* multiplexed mode values (sheet 2 of 2) symbol parameter min. max. units notes notes: 1. the ex_ale signal is extended form t to 4t nnsec, based on the programming of the t1 timing parameter. the parameter tale2addrhold is fixed at t. 2. setting the address phase parameter (t1) will adjust the duration that the address appears to the external device. 3. setting the data setup phase parameter (t2) will adj ust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. setting the data strobe phase parameter (t3) will adjust the duration that the data strobe appears (read or write) to an external device. data will be available during this time as well. 5. setting the data hold strobe phase parameter (t4) will adjust the duration that the chip selects, address, and data (during a write) will be held. 6. setting the recovery phase parameter (t5) will adj ust the duration between successive accesses on the expansion interface. 7. t is the period of the clock measured in ns. 8. clock to output delay for all si gnals will be a maximum of 15 ns for devices requi ring operation in synchronous mode. 9. timing was designed for a system load between 5pf and 60pf for high drive setting
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 147 figure 36. motorola* simplex mode table 70. motorola* simplex mode values (sheet 1 of 2) symbol parameter min. max. units notes t ad2valcs valid address to valid chip select 1 4 cycles 1 , 2 , 7 t dval2valds write data valid prior to exp_mot_ds_n falling edge 1 4 cycles 3 , 7 t dspulse pulse width of the exp_mot_ds_n 1 16 cycles 4 , 7 t dholdafterds valid data after the rising edge of exp_mot_ds_n 1 4 cycles 5 , 7 notes: 1. ex_ale is not valid in simplex mode of operation. 2. setting the address phase pa rameter (t1) will adjust th e duration that the addre ss appears to the external device. 3. setting the data setup phase parameter (t2) will adjust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. setting the data strobe phase parameter (t3) will adj ust the duration that the data strobe appears (read or write) to an external device. data will be available during th is time as well. 5. setting the data hold strobe phase parameter (t4) will adjust the duration that the chip selects, address, and data (during a write) will be held. 6. setting the recovery phase parameter (t5) will adj ust the duration between successive accesses on the expansion interface. 7. t is the period of the clock measured in ns. 8. clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. timing was designed for a system load between 5pf and 60pf for high drive setting a9588-01 ex_clk ex_addr ex_data ex_wr_n (exp_mot_ds_n) ex_rd_n (exp_mot_rnw) ex_data ex_rd_n (exp_mot_rnw) valid address output data t5 1-16 cycles t4 1-4 cycles ex_cs_n t dspulse t recov t ad2valcs t dval2valds input data t dhold2afterds t3 1-16 cycles t2 1-4 cycles t1 1-4 cycles ex_wr_n (exp_mot_ds_n) t rdsetup t rdhold
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 148 document number: 306261-003 t rdsetup data valid required before the rising edge of exp_mot_ds_n 5.3 14.7 ns t rdhold data hold required after the rising edge of exp_mot_ds_n 2ns t recov time required between successive accesses on the expansion interface. 116cycles 6 figure 37. hpi*?8 mode write accesses table 70. motorola* simplex mo de values (sheet 2 of 2) symbol parameter min. max. units notes notes: 1. ex_ale is not valid in simplex mode of operation. 2. setting the address phase parameter (t1) will adjust th e duration that t he address appears to the external device. 3. setting the data setup phase parameter (t2) will adjust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. setting the data strobe phase parameter (t3) will adjust the duration that the data strobe appears (read or write) to an external device. data wi ll be available during this time as well. 5. setting the data hold strobe phase parameter (t4) will ad just the duration that the chip selects, address, and data (during a write) will be held. 6. setting the recovery phase parameter (t5) will adjus t the duration between succ essive accesses on the expansion interface. 7. t is the period of the clock measured in ns. 8. clock to output delay for all si gnals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. timing was designed for a system load between 5pf and 60pf for high drive setting ex_addr[2:1] (hcntl) ex_addr[0] (hbil) ex_rdy_n (hrdy) data ex_data (hdin) ex_cs_n (hcs_n) ex_wr_n (hds1_n) ex_rd_n (hr_w_n) valid data valid ex_clk t1 t3 t4 t3 t2 t4 t5 t1 t2 t5 tadd_setup tcs2hds1val thds1_pulse tdata_setup tdata_hold trecov
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 149 table 71. hpi* timing symbol description state description min max unit notes t1 address timing 3 4 cycles 1, 5, 6 t2 setup/chip select timing 3 4 cycles 2, 6 t3 strobe timing 2 16 cycles 3, 5, 6 t4 hold timing 3 4 cycles 6 t5 recovery phase 2 17 cycles 6 table 72. hpi*?8 mode write accesses values symbol parameter min .max.unitsnotes t add_setup valid time that address is asserted on the line. the address is asserted at the same time as chip select. 11 45 cycles 1, 5, 6 t cs2hds1val delay from chip select being active and the hds1 data strobe being active. 3 4 cycles 5, 6 t hds1_pulse pulse width of the hds1 data strobe 4 5 cycles 2, 4, 5 t data_setup data valid prior to the rising edge of the hds1 data strobe. 4 5 cycles 3, 5, 6 t data_hold data valid after the rising edge of the hds1 data strobe. 4 36 cycles 3, 6 t recov time required between successive accesses on the expansion interface. 2 17 cycles 4, 6 notes: 1. the address phase parameter (t1) must be set to a mini mum value of 2. this value allows three t clocks for the address phase. this setting is required to ensure that in the event of an hrdy, the ixp45x/ ixp46x network processors have had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de-active. 2. the data setup phase parameter (t2) must be set to a minimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the ixp45x/ ixp46x network processors have had sufficient time to recogni ze the hrdy and hold the data setup phase for at least one clock puls e after the hrdy is de-active 4. setting the recovery phase parameter (t5) will adj ust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in the access. the interface will not leave states t1 or t3 until hrdy is de-active 6. one cycle is the period of the expansion bus clock. 7. timing was designed for a system load between 5 pf and 60 pf for high drive setting.
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 150 document number: 306261-003 table 73. setup/hold timing values in asynchronous mode of operation parameter min. max. units notes output valid after rising edge of ex_clk 10 ns 1 output hold after rising edge of ex_clk 0 ns 1 input setup prior to rising edge of ex_clk 3.5 ns 1 input hold required after rising edge of ex_clk 0.5 ns 1 notes: 1. the setup and hold timing values are for all modes. table 74. hpi*-16 multiplexed write accesses values symbol parameter min. max. units notes t add_setup valid time that address is asserted on the line. the address is asserted at the same time as chip select. 11 45 cycles 1, 5, 6 t cs2hds1val delay from chip select being active and the hds1 data strobe being active. 3 4 cycles 5, 6 t hds1_pulse pulse width of the hds1 data strobe 4 5 cycles 2, 4, 5 t data_setup data valid prior to the rising edge of the hds1 data strobe. 4 5 cycles 3, 5, 6 t data_hold data valid after the rising edge of the hds1 data strobe. 4 36 cycles 3, 6 t recov time required between successive accesses on the expansion interface. 217cycles4, 6 notes: 1. the address phase parameter (t1) must be set to a mini mum value of 2. this value allows three t clocks for the address phase. this setting is required to ensur e that in the event of an hrdy, the ixp45x/ixp46x network processors have had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse afte r the hrdy is de-active. 2. the data setup phase parameter (t2) must be set to a minimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the ixp45x/ixp46x network processors have had sufficient time to recognize the hrdy and hold the data setup phase for at least one clock pulse af ter the hrdy is de-active 4. setting the recovery phase parameter (t5) will adj ust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in the access. the interface will not leave states t1 or t3 until hrdy is de-active 6. one cycle is the period of the expansion bus clock. 7. timing was designed for a system load between 5pf and 60pf for high drive setting
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 151 figure 38. hpi*-16 multiplexed write mode table 75. hpi*-16 multiplexed read accesses values symbol parameter min. max. units notes t add_setup valid time that address is asserted on the line. the address is asserted at the same time as chip select. 11 45 cycles 1, 5, 6 t cs2hds1val delay from chip select being active and the hds1 data strobe being active. 3 4 cycles 5, 6 t hds1_pulse pulse width of the hds1 data strobe 4 5 cycles 2, 4, 5 t data_setup data is valid from the time from of the falling edge of hds1_n to when the data is read. 4 5 cycles 3, 5, 6 t recov time required between successive accesses on the expansion interface. 2 17 cycles 4, 6 notes: 1. the address phase parameter (t1) must be set to a mini mum value of 2. this value allows three t clocks for the address phase. this setting is required to ensure that in the event of an hrdy, the ixp45x/ ixp46x network processors have had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de-active. 2. the data setup phase parameter (t2) must be set to a minimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the ixp45x/ ixp46x network processors have had sufficient time to recogni ze the hrdy and hold the data setup phase for at least one clock puls e after the hrdy is de-active 4. setting the recovery phase parameter (t5) will adj ust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in the ac cess. the interface will not leave states t1 or t3 until hrdy is de-active 6. one cycle is the period of the expansion bus clock. 7. timing was designed for a system load between 5pf and 60pf for high drive setting data valid data valid t1 t3 t4 t3 t2 t4 t1 t2 t5 ex_addr[2:1] (hcntl) ex_rdy_n (hrdy) ex_data (hdin) ex_cs_n (hcs_n) ex_wr_n (hds1_n) ex_rd_n (hr_w_n) ex_clk tadd_setup thds1_pulse tcs2hds1val tdata_setup tdata_hold trecov
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 152 document number: 306261-003 figure 39. hpi*-16 multiplexed read mode valid valid data valid data t1 t3 t4 t3 t2 t4 t5 t1 t2 t5 ex_addr[2:1] (hcntl) ex_rdy_n (hrdy) ex_data (hdout) ex_cs_n (hcs_n) ex_wr_n (hds1_n) ex_rd_n (hr_w_n) ex_clk tadd_setup trecov thds1_pulse tdata_setup tcs2hds1val
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 153 table 76. hpi-16 non-multiplexed read accesses values symbol parameter min. max. units notes t add_setup valid time that address is asse rted on the line. the address is asserted at the same time as chip select. 11 45 cycles 1, 5, 6 t cs2hds1val delay from chip select being active and the hds1 data strobe being active. 3 4 cycles 5, 6 t hds1_pulse pulse width of the hds1 data strobe 4 5 cycles 2, 4, 5 t data_setup data is valid from the time from of the falling edge of hds1_n to when the data is read. 4 5 cycles 3, 5, 6 t recov time required between successive accesses on the expansion interface. 217cycles4, 6 notes: 1. the address phase parameter (t1) must be set to a mini mum value of 2. this value allows three t clocks for the address phase. this setting is required to ensure that in the event of an hrdy, the ixp45x/ixp46x network processors have had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de-active. 2. the data setup phase parameter (t2) must be set to a minimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a mi nimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the ixp45x/ixp46x network processors have had sufficient time to recognize t he hrdy and hold the data setup phase for at least one clock pulse after the hrdy is de-active 4. setting the recovery phase parameter (t5) will adj ust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in the a ccess. the interface will not leave states t1 or t3 until hrdy is de-active 6. one cycle is the period of the expansion bus clock. 7. timing was designed for a system load between 5pf and 60pf for high drive setting figure 40. hpi*-16 non-multiplexed read mode b-01 valid valid data valid data valid t1 t3 t4 t3 t2 t1 t2 t5 ex_addr[23:0] (ha) ex_rdy_n (hrdy) ex_data (hdout) ex_cs_n (hcs_n) ex_wr_n (hds1_n) ex_rd_n (hr_w_n) ex_clk tadd_setup tdata_setup thds1_pulse tcs2hds1val trecov
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 154 document number: 306261-003 table 77. hpi-16 non-multiple xed write accesses values symbol parameter min. max. units notes t add_setup valid time that address is as serted on the line. the address is asserted at the same time as chip select. 11 45 cycles 1, 5, 6 t cs2hds1val delay from chip select being active and the hds1 data strobe being active. 3 4 cycles 5, 6 t hds1_pulse pulse width of the hds1 data strobe 4 5 cycles 2, 4, 5 t data_setup data valid prior to the rising edge of the hds1 data strobe. 4 5 cycles 3, 5, 6 t data_hold data valid after the rising edge of the hds1 data strobe. 4 36 cycles 3, 6 t recov time required between successive accesses on the expansion interface. 217cycles4, 6 notes: 1. the address phase parameter (t1) must be set to a mini mum value of 2. this value allows three t clocks for the address phase. this setting is required to ensur e that in the event of an hrdy, the ixp45x/ixp46x network processors have had suffici ent time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de-active. 2. the data setup phase parameter (t2) must be set to a mi nimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the ixp45x/ixp46x network processors have had sufficient time to recognize the hrdy and hold the data setup phase for at least one clock pulse af ter the hrdy is de-active 4. setting the recovery phase parameter (t5) will adj ust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in the access. the interface will not leave states t1 or t3 until hrdy is de-active 6. one cycle is the period of the expansion bus clock. 7. timing was designed for a system load between 5 pf and 60 pf for high drive setting
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 155 figure 41. hpi*-16 non-multiplexed write mode data valid data valid t1 t3 t4 t3 t2 t4 t1 t2 t5 e x_addr[23:0] (ha) ex_rdy_n (hrdy) ex_data (hdin) ex_cs_n (hcs_n) ex_wr_n (hds1_n) ex_rd_n (hr_w_n) ex_clk tadd_setup trecov thds1_pulse tcs2hds1val tdata_setup tdata_hold
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 156 document number: 306261-003 5.6.2.7.3 using i/o wait the ex_iowait_n signal is available to be shared by devices attached to chip selects 0 through 7, when configured in intel or motorola modes of operation. the main purpose of this signal is to properly communicate w ith slower devices requiring more time to respond during data access. during idle cycles, the board is responsible for ensuring that ex_iowait_n is pulled-up. the expansion bus controller will always ignore ex_iowait_n for synchronous intel mode writes. for details, see the intel ? ixp45x and intel ? ixp46x product line of network processors developer?s manual , in the expansion bus controller chapter?s ?using i/o wait? section. figure 42. i/o wait normal phase timing note: notice that the access is an intel- style simplex read access. the data str obe phase is set to a value to last three clock cycles. the data is returned from the peripheral device prior to the three clocks and the peripheral device de-asserts ex_iowait_n. the data st robe phase terminates after two clocks even though the strobe phase was configured to pulse for three clocks. ex_ clk ex_cs_ n[0] ex_addr[23:0] ex_rd_n ex_data[15:0] valid data valid address 1 cycle 1 cycle 3 cycles 1 cycle t1=0 h t2=0 h t3=2h or 1h or 0h t4=0 h t5=0 h ex_ iowait_n b5242 -01 1 cycle 2 cycles
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 157 5.6.2.8 serial peripheral port interface timing figure 43. i/o wait extended phase timing figure 44. serial peripheral interface timing ex_ clk ex_cs_ n[0] ex_addr[23:0] ex_rd_n ex_data[15:0] valid data valid address 4 cycles 4 cycles 16 cycles 16 cycles t1=3 h t2=3 h t3=f h t4=3 h t5=f h ex_ iowait_n b5243- 01 .... 4 cycles ... . 2 cycles sspextclk sspsclk sspinputs sspoutputs t ov t is t ih t do v t do h
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 158 document number: 306261-003 5.6.2.9 i 2 c interface timing table 78. serial peripheral po rt interface timing values symbol parameter min. max. units notes t per_intclk minimum and maximum clock periods which can be produced by the ssp_sclk when the clock is being generated from the internal 3.7033mhz clock. .0072 1.8432 mhz t per_extclk minimum and maximum clock period which can be produced by the ssp_sclk when the clock is being generated from the externally supplied maximum clock rate of 33 mhz clock (ssp_extclk). .06445 16.5 mhz t is input setup time for data prior to the valid edge of ssp_sclk. these signals include ssp_srxd. 15 ns t ih input hold time for data after the to the valid edge of ssp_sclk. these signals include ssp_srxd. 0ns t dov ssp_sclk clock to output valid delay from output signals. these signals include ssp_stxd and ssp_sfrm. 16ns t doh output data hold valid from valid edge of ssp_sclk. these signals include ssp_stxd and ssp_sfrm. 1ns t ov output valid delay from ssp_extclk to ssp_sclk in external clock mode 215ns 1. timing was designed for a system load between 5pf and 40pf 2. clock jitter on the sspsclk is designed to be an av erage of the specified clock frequency. the sspsclk jitter specificati on is unspecified. figure 45. i 2 c interface timing table 79. i 2 c interface timing values (sheet 1 of 2) symbol parameter min. max. min. max. units notes f scl scl clock frequency 0 100 0 400 khz t buf bus free time between stop and start condition 4.7 1.3 s t hdsta hold time (repeated) start condition 4 0.6 s 2 t low scl clock low time 4.7 1.3 s 1 t high scl clock high time 4 0.6 s 1 notes: 1. not tested 2. after this period, the first clock pulse is generated i2c_sda i2c_scl stop start repeated start stop t buf t lo w t hdst a t sr t hddat t hi i g h t sudat t susta t sf t hdst a t sp t susto
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 159 t susta setup time for a repeated start condition 4.7 0.6 s t hddat data hold time 0 3.45 0 0.9 s t sudat data setup time 250 100 ns t sr scl and sda rise time 1000 20+0.1c b 300 ns t sf scl and sda fall time 300 20+0.1c b 300 ns t susto setup time for stop condition 4 0.6 s table 79. i 2 c interface timing values (sheet 2 of 2) symbol parameter min. max. min. max. units notes notes: 1. not tested 2. after this period, the fi rst clock pulse is generated
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 160 document number: 306261-003 5.6.2.10 high-speed, serial interfaces figure 46. high-speed, serial timings a9594-01 hss_txclk/ hss_rxclk 1 hss_(tx or rx)frame (positive edge) hss_(tx or rx)frame (negative edge) hss_ rxdata (positive edge) as inputs: valid data hss_ rxdata (negative edge) hss_(tx or rx)frame (positive edge) hss_(tx or rx)frame (negative edge) hss_ txdata (positive edge) hss_ txdata (negative edge) as outputs: valid data t1 t3 t4 valid data valid data t6 t5 t7 t8 t2 t9
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 161 table 80. high-speed, serial timing values symbol parameter min. max. units notes t1 setup time of hss_txframe, hss_rxframe, and hss_rxdata prior to the rising edge of clock 5ns 1 , 2 , 3 t2 hold time of hss_txframe, hss_rxframe, and hss_rxdata after the rising edge of clock 0ns 1 , 2 , 3 t3 setup time of hss_txframe, hss_rxframe, and hss_rxdata prior to the falling edge of clock 5ns 1 , 2 , 3 t4 hold time of hss_txframe, hss_rxframe, and hss_rxdata after the falling edge of clock 0ns 1 , 2 , 3 t5 rising edge of clock to output delay for hss_txframe, hss_rxframe, and hss_txdata 15 ns 1 , 4 t6 falling edge of clock to output delay for hss_txframe, hss_rxframe, and hss_txdata 15 ns 1 , 3 , 4 t7 output hold delay after rising edge of final clock for hss_txframe, hss_rxframe, and hss_txdata 0ns 1 , 3 , 4 t8 output hold delay after fa lling edge of fi nal clock for hss_txframe, hss_rxframe, and hss_txdata 0ns 1 , 3 , 4 t9 hss_txclk period and hss_rxclk period 1/8.192 mhz 1/512 khz ns 5 notes: 1. hss_txclk and hss_rxclk may be coming from external independent sources or being driven by the ixp45x/ixp46x network processors. the signals are shown to be synchronous for illustrative purposes and are not required to be synchronous. 2. applicable when the hss_rxframe and hss_txframe signals are being driven by an external source as inputs into the ixp45x/ixp46x network proc essors. always applicable to hss_rxdata. 3. the hss_rxframe and hss_txframe can be configured to accept data on the rising or falling edge of the given reference clock. hss_rxframe and hss_rx data signals are synchronous to hss_rxclk and hss_txframe and hss_txdata signals are synchronous to the hss_txclk. 4. applicable when the hss_rxframe and hss_txfram e signals are being driven by the ixp45x/ixp46x network processors to an external s ource. always applicable to hss_txdata. 5. the hss_txclk can be configured to be driven by an external source or be driven by the ixp45x/ixp46x network processors. the slowest cloc k speed that can be accepted or dr iven is 512 khz. the maximum clock speed that can be accepted or driven is 8.192 mhz. the clock duty cy cle accepted will be 50/50 + 20%. 6. timing was designed for a system load between 5 pf and 30 pf for high drive setting
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 162 document number: 306261-003 5.6.2.11 jtag figure 47. boundary-scan general timings figure 48. boundary-scan reset timings table 81. boundary-scan interface timings values symbol parameter conditions min. typ. max. units notes t bscl jtg_tck low time 50 ns 2 t bsch jtg_tck high time 50 ns 2 t bsis jtg_tdi, jtg_tms setup time to rising edge of jtg_tck 10 ns t bsih jtg_tdi, jtg_tms hold time from rising edge of jtg_tck 10 ns t bsoh jtg_tdo hold time after falling edge of jtg_tck 1.5 ns 1 t bsod jtg_tdo clock to output from falling edge of jtg_tck 40 ns 1 t bsr jtg_trst_n reset period 30 ns t bsrs jtg_tms setup time to rising edge of jtg_trst_n 10 ns t bsrh jtg_tms hold time from rising edge of jtg_trst_n 10 ns notes: 1. tests completed with a 40-pf load to ground on jtag_tdo. 2. jtg_tck may be stopped indefinitely in either the low or high phase. b0416-01 t bsel t bsis t bsih t bsch jtg_tck jtg_tms, jtg_tdi jtg_tdo t bsoh t bsod a9597-01 t bsr t bsrs t bsrh jtg_trst_n jtg_tms
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 163 5.6.3 reset timings figure 49. reset timings table 82. reset timings table parameters symbol parameter min. typ. max. units note t release_pwon_rst_n minimum time required to hold the pwon_rst_n at logic 0 state after stable power has been applied to the ixp45x/ ixp46x network processors. 500 ms 1 t release_reset_in_n minimum time required to hold the reset_in_n at logic 0 state after pwon_rst_n has been released to a logic 1 state. the reset_in_n signal must be held low when the pwon_rst_n signal is held low. 10 ns t pll_lock maximum time for pll_lock signal to drive to logic 1 after reset_in_n is driven to logic 1 state. the boot sequence does not occur until this period is complete. 10 s t ex_addr_setup minimum time for the ex_addr signals to drive the inputs prior to reset_in_n being driven to logic 1 state. this is used for sampling configuration information. 50 ns 2 t ex_addr_hold minimum/maximum time for the ex_addr signals to drive the inputs prior to pll_lock being driven to logic 1 state. this is used for sampling configuration information. 020ns 2 t warm_reset minimum time required to dr ive reset_in_n signal to logic 0 in order to cause a reset after the ixp45x/ixp46x network processors have been in normal operation. the power must remain stable and the pwon_rst_n signal must remain stable. 500 ns notes: 1. t release_pwron_rst_n is the time required for the internal oscillator to reach stability. when an exte rnal oscillator is being used the 500-ms delay is not required. 2. the expansion bus address is captur ed as a derivative of the reset_in_n si gnal going high. when a programmable-logic device is used to drive the ex_addr signals instead of pull- downs, the signals must be acti ve until pll_lock is active. v ccp v ccm v cc pll_lock pwron_reset_n reset_in_n ex_addr[24:0] ex_addr[24:0]-pull up/down cfg settings to be captured cfg settings to be captured ixp46x drives outputs t release_pwron_rst_n t ex_addr_setup t release_rst_n t pll_lock t ex_addr_hold
electrical specifications august 2005 intel ? ixp45x and intel ? ixp46x product line of network processors datasheet 164 document number: 306261-003 5.7 power sequence the 3.3-v i/o voltage (v ccp ) and the 2.5-v i/o voltage (v ccm) must be powered up at least 1 s before the core voltage (v cc ). the ixp45x/ixp46x network processors core voltage (v cc ) must never become stable prior to the 3.3-v i/o voltage (v ccp ) or the 2.5-v i/o voltage (v ccm ). sequencing between v ccp and v ccm can occur in any order with respect to one another. t io_phase can be: ? v ccp prior to v ccm ? v ccm prior to v ccp ? v ccp simultaneously to v ccm the v ccosc , v ccpll1 , v ccpll2, and v ccpll3 voltages follow the v cc power-up pattern. the v ccoscp follows the v ccp power-up pattern. the value for t power_up must be at least 1 s before the later of v ccp and v ccm . the t power_up timing parameter is measured between the later of the i/o power rails (v ccp at 3.3 v or v ccm at 2.5 v) and v cc at 1.3 v. figure 50. power-up sequence timing volts 1 2 3 4 time v ccp v cc v ccm t io_phase t power_up
electrical specifications intel ? ixp45x and intel ? ixp46x product line of network processors datasheet august 2005 document number: 306261-003 165 5.8 power dissipation the intel ? ixp45x and intel ? ixp46x product line of network processors were tested assuming a typical worst case networking application under a tester environment. the following power assessments in table 83 assume this typical worst case netw orking application using the interface activity factors listed in table 84 . the actual power may vary if interface activity factors are different from table 84 . if applications do not require use of certain peripherals or if interfaces operate at lower activity factors, then the power required by the part may be significantly less than the numbers stated in table 83 . activity factor is directly pro portional to the overal l power consumption wh ere each application will have a different activity fact or and different power conclusion. table 84 illustrates the activity factor of each interface on the tester during the typical wors t case networking application. 5.9 ordering information for ordering information, please contact your local intel sales representative. table 83. power dissipation values part type power rail icc (ma) power per rail (mw)? maximum power dissipation (watts) intel ? ixp45x and intel ? ixp46x product line of network processors? 266 mhz 3.3 v 88 305 2.8 2.5 v 255 669 1.3 v 1335 1822 intel ? ixp45x and intel ? ixp46x product line of network processors ? 400 mhz 3.3 v 88 305 3.0 2.5 v 255 669 1.3 v 1485 2027 intel ? ixp45x and intel ? ixp46x product line of network processors ? 533 mhz 3.3 v 88 305 3.2 2.5 v 255 669 1.3 v 1630 2225 intel ? ixp46x product line ? 667 mhz 3.3 v 88 305 4.0 2.5 v 255 669 1.5 v 1920 3024 ? power in mw is calculated using maximu m vcc specification for each power rail. table 84. power dissipation test conditions interface ddr (data/addr) pci (addr/cntl) exp (data/cntl) ethernet (data) utopia (data) activity factor 15% / 6% 16% / 10% 5% / 3.7% 20% 17% notes: 1. all output clocks toggling at their specified rate. 2. tester did not include termination resi stors on any interface for power analysis. 3. tester measures power at 85 degrees f ambient. 4. current measurements are average and not peak. 5. intel xscale ? core processor tested running dsp software.

▲Up To Search▲

Price & Availability of GWIXP455AAC

	To Download GWIXP455AAC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .